公开(公告)号：US08552570B2

公开(公告)日：2013-10-08

申请号：US12811733

申请日：2009-01-06

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC分类号： H01L29/40

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

摘要翻译： 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US07880295B2

公开(公告)日：2011-02-01

申请号：US12618399

申请日：2009-11-13

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

摘要翻译： 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US20100295191A1

公开(公告)日：2010-11-25

申请号：US12811733

申请日：2009-01-06

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC分类号： H01L23/49 ,  H01L21/60 ,  H05K1/11 ,  H01R43/00

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

摘要翻译： 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US07652375B2

公开(公告)日：2010-01-26

申请号：US11790155

申请日：2007-04-24

申请人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

摘要翻译： 第一电子电路部件和第二电子电路部件分别经由第一焊料和第二焊料电连接到导电部件。 导电构件形成在树脂膜中。 导电构件被构造成包含第二扩散阻挡金属膜。 第二扩散阻挡金属膜防止第二焊料的扩散。 在导电构件和第一焊料之间设置有第一扩散阻挡金属膜。 第一扩散阻挡金属膜防止第一焊料的扩散。 在树脂膜的第一表面和导电部件上形成粘接金属膜，以与树脂膜和导电部件接触。 粘合金属膜比第一焊料和第一扩散阻挡金属膜中的任一种具有比树脂膜更强的粘附性。

公开(公告)号：US20090072404A1

公开(公告)日：2009-03-19

申请号：US12210702

申请日：2008-09-15

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/29099 ,  H01L2924/00

摘要： A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal.

摘要翻译： 在非常小的通孔中确保连接可靠性的高度可靠的半导体器件包括：半导体衬底; 放置在半导体衬底上并具有一个或多个第一布线层，一个或多个绝缘层和第一通孔的第一布线结构; 放置在第一布线结构上并具有一个或多个第二布线层，一个或多个第二绝缘层，第二通孔和第三通孔的第二布线结构; 以及设置在第二布线结构上的外部端子。 连接到第二布线结构的第二布线层和外部端子的第二通孔具有布置在位于外部端子一侧的通孔的端部处的连接接口。

公开(公告)号：US08815678B2

公开(公告)日：2014-08-26

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/8242 ,  H01L21/316 ,  H01L49/02 ,  C23C16/455 ,  G11C11/404 ,  H01L21/314 ,  H01L27/108 ,  C23C16/40

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US08212299B2

公开(公告)日：2012-07-03

申请号：US10170813

申请日：2002-06-13

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1−x)O2(0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US20120119338A1

公开(公告)日：2012-05-17

申请号：US13200944

申请日：2011-10-05

申请人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

发明人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

IPC分类号： H01L23/552 ,  H01L21/02

CPC分类号： H01L23/58 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/97 ,  H01L27/224 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2916 ,  H01L2224/2919 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/1435 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

摘要翻译： 半导体芯片包括磁存储装置，并且在第一面上包括电极焊盘。 至少在电极焊盘露出的状态下，半导体芯片被覆有磁屏蔽层。 半导体芯片通过凸块安装在互连基板上。 半导体芯片和互连基板中的至少一个包括凸部，并且凸块设置在凸部上。

公开(公告)号：US08169013B2

公开(公告)日：2012-05-01

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0

公开(公告)号：US20060192287A1

公开(公告)日：2006-08-31

申请号：US11341445

申请日：2006-01-30

申请人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

发明人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

IPC分类号： H01L23/52

CPC分类号： H05K3/205 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/107 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate comprises a first interconnection pattern formed of the first interconnection which comprises at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

摘要翻译： 互连基板设置有在底面具有下沉部分的基底绝缘膜，设置在凹陷部分中的第一互连，形成在基底绝缘膜中的通孔，以及连接到第一互连件的第二互连 通过所述通孔内的导体，并形成在所述基底绝缘膜的顶表面上，其中所述互连衬底包括由所述第一互连形成的第一互连图案，所述第一互连图案至少包括沿着与第一互连正交的第二方向延伸的线状图案 第一方向和翘曲控制图案，其设置在基底绝缘膜的底面的下沉部分中，并且形成为抑制互连基板朝向底部绝缘膜两侧的底侧的翘曲 第一个方向