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    Preparation method of a germanium-based schottky junction
    71.
    发明授权
    Preparation method of a germanium-based schottky junction 有权
    锗基肖特基结的制备方法

    公开(公告)号：US09484208B2

    公开(公告)日：2016-11-01

    申请号：US14380026

    申请日：2013-09-30

    申请人： Peking University

    发明人： Ru Huang ,  Meng Lin ,  Zhiqiang Li ,  Xia An ,  Ming Li ,  Quanxin Yun ,  Min Li ,  Pengqiang Liu ,  Xing Zhang

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/812 ,  H01L29/66 ,  H01L29/80 ,  H01L29/872 ,  H01L21/02 ,  H01L21/3213

    CPC分类号： H01L21/28537 ,  H01L21/02052 ,  H01L21/02192 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28568 ,  H01L21/3213 ,  H01L29/66143 ,  H01L29/66848 ,  H01L29/806 ,  H01L29/812 ,  H01L29/872

    摘要： The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.

    摘要翻译： 本发明公开了一种基于锗的肖特基结的制备方法，包括：清洗N型锗基基材的表面，然后在表面上沉积一层CeO 2，并进一步沉积一层金属。 稀土氧化物CeO2与锗衬底接触后，Ce-O-Ge键的稳定性可以在界面形成，有利于降低界面态密度，提高界面质量，降低MIGS和 抑制费米级钉扎。 同时，与Si3N4，Al2O3，Ge3N4等的情况相比，金属和锗衬底之间的CeO 2引入的隧穿电阻较小。 鉴于相对于锗衬底的优异的表面特性和较小的导带偏移，CeO 2电介质层的插入适用于制备具有低电阻率的锗基肖特基结。

    JFET devices with increased barrier height and methods of making the same
    75.
    发明授权
    JFET devices with increased barrier height and methods of making the same 有权
    具有增加势垒高度的JFET器件及其制造方法

    公开(公告)号：US08723235B2

    公开(公告)日：2014-05-13

    申请号：US13400442

    申请日：2012-02-20

    申请人： Chandra Mouli

    发明人： Chandra Mouli

    IPC分类号： H01L29/812

    CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66848 ,  H01L29/66916 ,  H01L29/808 ,  H01L29/812 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

    摘要： Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

    摘要翻译： 提供了提供具有改进的操作特性的JFET晶体管的器件和方法。 具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。 例如，一个或多个实施例包括具有掺杂碳化硅栅极的JFET，而其他实施例包括具有金属栅极的JFET。 一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

    METHOD FOR MAKING TRANSISTORS
    76.
    发明申请
    METHOD FOR MAKING TRANSISTORS 失效
    制造晶体管的方法

    公开(公告)号：US20130270615A1

    公开(公告)日：2013-10-17

    申请号：US13508731

    申请日：2011-09-28

    申请人： Dongping Wu ,  Jun Luo ,  Yinghua Piao ,  Zhiwei Zhu ,  Shili Zhang ,  Wei Zhang

    发明人： Dongping Wu ,  Jun Luo ,  Yinghua Piao ,  Zhiwei Zhu ,  Shili Zhang ,  Wei Zhang

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7839 ,  H01L29/6653 ,  H01L29/66848

    摘要： A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.

    摘要翻译： 一种制造晶体管的方法，包括：提供半导体衬底; 在所述半导体衬底上形成栅叠层; 在半导体衬底上形成绝缘层; 在绝缘层上形成耗尽层; 蚀刻耗尽层和绝缘层; 在所述半导体衬底上形成金属层; 进行热退火; 并去除金属层。 作为本发明的优点，每个侧壁的上部外侧部分包括能够与金属层反应的材料，从而在退火过程中吸收侧壁两侧的金属，从而防止金属朝向 半导体层，并且确保形成的肖特基结可以是超薄和均匀的，并且具有可控和抑制的横向生长。

    INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
    77.
    发明申请
    INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL 有权
    绝缘栅栏场效应晶体管有通道的肖特基屏障

    公开(公告)号：US20130140629A1

    公开(公告)日：2013-06-06

    申请号：US13757597

    申请日：2013-02-01

    申请人： Acorn Technologies, Inc.

    发明人： Daniel E. Grupp ,  Daniel J. Connelly

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

    摘要： A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

    摘要翻译： 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。 通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。 钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下面的底切空隙区域 。 金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。

    Semiconductor device with a pillar region and method of forming the same
    78.
    发明授权
    Semiconductor device with a pillar region and method of forming the same 有权
    具有柱区域的半导体器件及其形成方法

    公开(公告)号：US08415737B2

    公开(公告)日：2013-04-09

    申请号：US11765252

    申请日：2007-06-19

    申请人： Berinder P. S. Brar ,  Wonill Ha

    发明人： Berinder P. S. Brar ,  Wonill Ha

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823487 ,  H01L29/66848 ,  H01L29/8122 ,  H01L29/872

    摘要： A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

    摘要翻译： 半导体器件，其形成方法以及包括半导体器件的功率转换器。 在一个实施例中，半导体器件包括重掺杂衬底，重掺杂衬底下面的源极/漏极接触以及重掺杂衬底之上的沟道层。 半导体器件还包括在沟道层上方的重掺杂源极/漏极层以及重掺杂源极/漏极层上方的另一个源极/漏极接触。 该半导体器件还包括通过另一个源/漏接触，重掺杂源/漏层和沟道层的部分的柱区域，以在其间形成垂直单元。 半导体器件的非导电区域位于沟道层的部分中。 半导体器件还包括在柱状区域中的非导电区域之上的栅极。 半导体器件还可以包括包括沟道层和肖特基接触的肖特基二极管。

    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure
    79.
    发明申请
    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure 失效
    具有外延生长门结构的结场效应晶体管

    公开(公告)号：US20120256238A1

    公开(公告)日：2012-10-11

    申请号：US13080690

    申请日：2011-04-06

    申请人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/808 ,  H01L21/337

    CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

    摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。