公开(公告)号：US20130037935A1

公开(公告)日：2013-02-14

申请号：US13205864

申请日：2011-08-09

Applicant: Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

Inventor： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L21/76898 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1184 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

Abstract translation: 本发明涉及一种用于半导体器件的封装以及用于将整个半导体芯片整体封装在模塑料中的制造方法。 在半封装器件封装中，通过利用再分配技术，分布在芯片顶部的焊盘重新分布到位于介质层中的再分布焊盘的阵列中。 半导体芯片的顶部上的电极或信号端子通过填充在半导体晶片的硅衬底中形成的通孔中的导电材料连接到芯片底部的电极金属段。 此外，顶部模制部分和底部模制部分完全密封半导体芯片，从而提供最佳的机械和电气保护。

公开(公告)号：US08344499B2

公开(公告)日：2013-01-01

申请号：US13421864

申请日：2012-03-16

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L29/78

CPC classification number: H01L23/49562 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/83191 ,  H01L2224/8485 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/01028 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract translation: 一种制造芯片暴露半导体封装的方法，包括以下步骤：在晶片上的每个芯片的正面上电镀多个电极; 研磨晶片的背面并沉积后金属，然后分离每个芯片; 安装具有粘附在引线框架的多个桨叶的前面上的电镀电极的芯片; 将胶带粘附在背面金属上并用模塑料包封; 移除带子并穿过引线框架和模塑料形成多个封装的半导体器件。

公开(公告)号：US20120299119A1

公开(公告)日：2012-11-29

申请号：US13118445

申请日：2011-05-29

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC: H01L27/088 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract translation: 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US08283212B2

公开(公告)日：2012-10-09

申请号：US12980309

申请日：2010-12-28

Applicant: Yan Xun Xue ,  Jun Lu ,  Anup Bhalla

Inventor： Yan Xun Xue ,  Jun Lu ,  Anup Bhalla

IPC: H01L21/00 ,  H01L21/60

CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for making a wire bond package comprising the step of providing a lead frame array comprising a plurality of lead frame units therein, each lead frame unit comprises a first die pad and a second die pad each having a plurality of tie bars connected to the lead frame array, a plurality of reinforced bars interconnecting the first and second die pads; the reinforced bars are removed after molding compound encapsulation.

Abstract translation: 一种用于制造引线接合封装的方法，包括提供包括多个引线框架单元的引线框架阵列的步骤，每个引线框架单元包括第一管芯焊盘和第二管芯焊盘，每个引线框架单元具有连接到 引线框架阵列，互连第一和第二管芯焊盘的多个加强杆; 在模塑复合材料封装之后去除增强棒。

公开(公告)号：US20120164793A1

公开(公告)日：2012-06-28

申请号：US13045407

申请日：2011-03-10

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56

CPC classification number: H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/83

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US20110062506A1

公开(公告)日：2011-03-17

申请号：US12947107

申请日：2010-11-16

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L27/06

CPC classification number: H01L23/5223 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

Abstract translation: 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US20110059593A1

公开(公告)日：2011-03-10

申请号：US12947717

申请日：2010-11-16

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L21/02

CPC classification number: H01L23/5223 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0688 ,  H01L28/88 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

Abstract translation: 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US20160155688A9

公开(公告)日：2016-06-02

申请号：US14033140

申请日：2013-09-20

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

公开(公告)号：US09184117B2

公开(公告)日：2015-11-10

申请号：US13663694

申请日：2012-10-30

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L29/40 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract translation: 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US09054091B2

公开(公告)日：2015-06-09

申请号：US13913770

申请日：2013-06-10

Applicant: Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

Inventor： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Peter Wilson ,  Yan Huo ,  Zhiqiang Niu ,  Ming-Chen Lu

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/02 ,  H01L23/34 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73104 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract translation: 一种混合封装多芯片半导体器件，包括引线框单元，第一半导体芯片，第二半导体芯片，第一互连结构和第二互连结构，其中第一半导体芯片附接在第一裸片上，第二半导体 芯片被翻转并附接在第三引脚和第二管芯焊盘上，第一互连结构电连接第一半导体芯片的前表面处的第一电极和第二半导体芯片的后表面处的第三电极和第二电极 在第一半导体芯片的前表面通过第二互连结构电连接。