公开(公告)号：US20170194251A1

公开(公告)日：2017-07-06

申请号：US15466380

申请日：2017-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Juntao LI

IPC: H01L23/525 ,  H01C17/00 ,  H01L21/8234 ,  H01H69/02

CPC classification number: H01L23/5256 ,  H01C17/006 ,  H01H69/022 ,  H01L21/31051 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

公开(公告)号：US20170141184A1

公开(公告)日：2017-05-18

申请号：US15417932

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Christopher J. PENNY ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/88 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53228 ,  H01L28/60 ,  H01L28/82

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

公开(公告)号：US20170140995A1

公开(公告)日：2017-05-18

申请号：US15417597

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/785

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US20170117193A1

公开(公告)日：2017-04-27

申请号：US15398827

申请日：2017-01-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Balasubramanian PRANATHARTHIHARAN ,  Soon-Cheon SEO

IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/08 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/0257 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

公开(公告)号：US20170084681A1

公开(公告)日：2017-03-23

申请号：US14861511

申请日：2015-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/87 ,  H01L28/88 ,  H01L28/91 ,  H01L28/92

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

公开(公告)号：US20160365312A1

公开(公告)日：2016-12-15

申请号：US14736881

申请日：2015-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Christopher J. PENNY ,  Theodorus E. STANDAERT ,  Junli WANG

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/88 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53228 ,  H01L28/60 ,  H01L28/82

Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

Abstract translation: 提供了后端（BEOL）电容器和制造方法。 该方法包括在基板上形成布线，相邻布线之间具有间隔。 该方法还包括通过沉积封盖材料在相邻布线之间的间隔内形成气隙。 该方法还包括打开选定的相邻布线之间的气隙。 所述方法还包括在所述打开的气隙中沉积导电材料。

公开(公告)号：US20160254350A1

公开(公告)日：2016-09-01

申请号：US15152249

申请日：2016-05-11

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Pouya HASHEMI ,  Ali KHAKIFIROOZ ,  Alexander REZNICEK

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02208 ,  H01L21/02293 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785

Abstract: A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk substrate. The material stack and a portion of the bulk substrate are then patterned by etching to provide an intermediate fin structure including a base semiconductor portion and alternating portions of the silicon etch stop material and the germanium nanowire template material. After recessing each germanium nanowire template material and optionally the base semiconductor portion, and etching each silicon etch stop material to define a new fin structure, a spacer is formed on sidewall surfaces of the remaining portions of the new fin structure. The alternating layers of germanium nanowire template material are then suspended above a notched surface portion of the bulk substrate and thereafter a functional gate structure is formed.

Abstract translation: 包括硅蚀刻停止材料和锗纳米线模板材料的交替层的材料堆叠形成在本体衬底的表面上。 然后通过蚀刻对材料堆叠和体基板的一部分进行构图，以提供包括基底半导体部分和硅蚀刻停止材料和锗纳米线模板材料的交替部分的中间翅片结构。 在每个锗纳米线模板材料和任选的基底半导体部分凹陷之后，并且蚀刻每个硅蚀刻停止材料以限定新的鳍结构，在新的鳍结构的其余部分的侧壁表面上形成间隔物。 然后将锗纳米线模板材料的交替层悬浮在本体衬底的缺口表面部分上方，然后形成功能栅极结构。

公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。

公开(公告)号：US20160172448A1

公开(公告)日：2016-06-16

申请号：US15048709

申请日：2016-02-19

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Bruce B. DORIS ,  Hong HE ,  Ali KHAKIFIROOZ

IPC: H01L29/161 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7851

Abstract: A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.

公开(公告)号：US20160064288A1

公开(公告)日：2016-03-03

申请号：US14470347

申请日：2014-08-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Bruce B. DORIS ,  Pouya HASHEMI ,  Ali KHAKIFIROOZ ,  Alexander REZNICEK

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66795 ,  H01L29/785

Abstract: Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

Abstract translation: 硅片形成在体硅衬底中，其后在每个硅片之间形成沟槽隔离区。 nFET和pFET器件区域中的硅散热片然后凹入。 在每个凹陷硅片部分的最上表面上或在基底的暴露表面上形成松弛的硅锗合金翅片部分。 在pFET器件区域内的每个松弛的硅锗合金翅片部分上形成压缩应变硅锗合金翅片部分，并且在nFET器件区域内的每个松弛硅锗合金翅片部分上形成应变含硅鳍部分。 然后暴露每个压缩应变含硅锗合金翅片部分和每个拉伸应变含硅翅片部分的侧壁表面。 在每个压缩应变含硅锗合金翅片部分和每个拉伸应变含硅翅片部分的暴露的侧壁表面上设置功能门结构。