公开(公告)号：US20070108568A1

公开(公告)日：2007-05-17

申请号：US11382983

申请日：2006-05-12

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey Punzalan ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49555 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.

摘要翻译： 提供集成电路封装到封装堆叠系统，包括提供第一集成电路封装，具有构造的引线框架，提供具有所配置的引线框架的第二集成电路封装，以及通过电连接所配置的引线框，形成集成电路封装对 第一集成电路封装到第二集成电路封装的配置的引线框架。

公开(公告)号：US20060186514A1

公开(公告)日：2006-08-24

申请号：US11163770

申请日：2005-10-29

申请人： IL Kwon Shim ,  Ming Ying ,  Seng Guan Chow

发明人： IL Kwon Shim ,  Ming Ying ,  Seng Guan Chow

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The present invention provides a package stacking lead frame system comprising forming a lead frame interposer including a dual row of terminal leads positioned around a die attach pad, mounting a first die on the die attach pad, wherein the first die is connected to the dual row of terminal leads, molding a molding compound around the first die and the dual row of terminal leads and mounting a second integrated circuit package on the lead frame interposer, wherein the second integrated circuit package size is independent of the first die size.

摘要翻译： 本发明提供了一种封装堆叠引线框架系统，包括形成引线框架插入件，该引线框架插入件包括位于管芯附接垫周围的双排端子引线，将第一管芯安装在管芯附着垫上，其中第一管芯连接到双列 的端子引线，围绕第一管芯和双列端子引线成型模塑料，并将第二集成电路封装件安装在引线框架插入件上，其中第二集成电路封装尺寸独立于第一管芯尺寸。

公开(公告)号：US09299648B2

公开(公告)日：2016-03-29

申请号：US12714291

申请日：2010-02-26

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/02 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/105 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有元件侧和系统侧的封装基板; 在所述封装衬底的所述元件侧上沉积阻焊层; 在阻焊层中形成存取开口的组和模具安装开口; 将集成电路管芯安装在管芯安装口中; 在所述进入开口中形成导电触点; 以及将系统互连件附接到封装衬底的系统侧，包括通过阻焊层控制系统互连的共面性。

公开(公告)号：US08999754B2

公开(公告)日：2015-04-07

申请号：US13463148

申请日：2012-05-03

申请人： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han

发明人： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han

IPC分类号： H01L21/00 ,  H01L23/02 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L23/00

CPC分类号： H01L23/3128 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer.

摘要翻译： 一种集成电路封装系统，包括基底基板，在基底基板上附着基模，将具有中介层电路器件的集成插入件安装在基模上，以及在集成插入件上形成具有密封腔的封装系统密封剂。

公开(公告)号：US08846454B2

公开(公告)日：2014-09-30

申请号：US13555531

申请日：2012-07-23

申请人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L21/44 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L25/16 ,  H01L25/10 ,  H01L23/50 ,  H05K3/46

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

摘要翻译： 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US08643163B2

公开(公告)日：2014-02-04

申请号：US12371730

申请日：2009-02-16

申请人： Il Kwon Shim ,  Byung Joon Han ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Byung Joon Han ,  Seng Guan Chow

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package-on-package stacking system includes: providing a first integrated circuit package, mounting a metalized interposer substrate over the first integrated circuit package, attaching a stiffener integrated with the metalized interposer substrate and having dimensions within package extents, and attaching a second integrated circuit package on the metalized interposer substrate adjacent the stiffener.

摘要翻译： 集成电路封装堆叠堆叠系统包括：提供第一集成电路封装，将金属化插入器基板安装在第一集成电路封装上，附接与金属化插入器基板集成的加强件并具有尺寸在封装范围内， 第二集成电路封装在与加强件相邻的金属化插入器基板上。

公开(公告)号：US08604602B2

公开(公告)日：2013-12-10

申请号：US12777415

申请日：2010-05-11

申请人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Youngcheol Kim

发明人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Youngcheol Kim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/00

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.

摘要翻译： 一种集成电路封装系统的制造方法，包括：制造具有元件侧和系统侧的基底封装基板; 在组件侧耦合堆叠互连; 以及形成用于接收集成电路器件的集成电路插座，通过在组件侧上模制增强的密封剂并暴露所述堆叠互连的一部分。

公开(公告)号：US20120223426A9

公开(公告)日：2012-09-06

申请号：US13248312

申请日：2011-09-29

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L23/562 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

公开(公告)号：US20120217634A9

公开(公告)日：2012-08-30

申请号：US13038843

申请日：2011-03-02

申请人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L23/485

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/187 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

摘要翻译： 半导体器件包括具有多个凸块的第一半导体管芯或部件，以及多个第一和第二接触焊盘。 在一个实施例中，第一和第二接触垫包括可湿性接触垫。 凸块直接安装在第一接触焊盘的第一表面上，以对准第一半导体管芯或部件。 密封剂沉积在第一半导体管芯或部件上。 互连结构形成在密封剂上方并连接到与第一接触焊盘的第一表面相对的第一和第二接触焊盘的第二表面。 通过密封剂形成多个通孔并延伸到第二接触焊盘的第一表面。 导电材料沉积在通孔中以形成多个导电通孔，其通过第二接触焊盘对准以减少互连间距。

公开(公告)号：US20120199971A1

公开(公告)日：2012-08-09

申请号：US13446741

申请日：2012-04-13

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

摘要翻译： 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个包括围绕腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框互连结构电连接到裸片。