公开(公告)号：US06891761B2

公开(公告)日：2005-05-10

申请号：US10767053

申请日：2004-01-30

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Michihiro Mishima ,  Katsuyuki Nakanishi

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Michihiro Mishima ,  Katsuyuki Nakanishi

IPC分类号： H01L21/76 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  G11C16/06

CPC分类号： H01L29/7842 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/10873 ,  H01L27/10897

摘要： A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.

摘要翻译： 提供一种半导体器件，其包括使用期望具有相同特性的两个或更多个场效应晶体管的电路，能够实现高可靠性和优异的晶体管特性。 期望具有相同特性的晶体管被​​放置在半导体器件中，以具有相同的STI沟槽宽度（与形成晶体管的有源区相邻的浅沟槽隔离的宽度）。 通过这样的组成，由于浅沟槽隔离而在有源区中生长的应力在晶体管之间被均衡，从而可以使晶体管的特性相等。

公开(公告)号：US06883746B2

公开(公告)日：2005-04-26

申请号：US10250550

申请日：2001-01-04

申请人： Atsumi Murachi ,  Hideo Miura ,  Takashi Nakamura

发明人： Atsumi Murachi ,  Hideo Miura ,  Takashi Nakamura

IPC分类号： B65H18/04 ,  B65H75/24 ,  B65H18/10

CPC分类号： B65H18/04 ,  B65H75/243 ,  B65H2301/4148 ,  B65H2403/731

摘要： A winding device, comprising a ring-shaped holder disposed concentrically with a winding shaft, a ring-shaped slider fitted onto the outer peripheral surface of the holder, and a plurality of chips disposed at angular intervals on a tapered inclined surface formed on the outer peripheral surface of the slider, wherein a fluid pressure passes through a first flow path in the winding shaft, the slider is moved in the axial direction of the winding shaft by a first piston, each chip is moved in the radial direction of the winding shaft by the inclination surface of the slider and pressed against the inner peripheral surface of the winding core so as to hold the winding core, a second piston is pressed against the end face of the holder by a second flow path independent of the first flow path, and the torque of the winding shaft is transmitted to the holder, slider, chips, and winding core by the friction between the second piston and the holder so as to rotate the winding core.

摘要翻译： 一种卷绕装置，包括与卷绕轴同心地设置的环形保持器，安装在保持器的外周面上的环状滑块，和以角度间隔设置在形成于外侧的锥形倾斜面上的多个芯片 滑块的外周面，其中流体压力通过卷绕轴中的第一流路，滑块通过第一活塞沿着卷绕轴的轴向移动，每个芯片沿着卷绕轴的径向方向移动 通过滑动件的倾斜表面并压靠在卷芯的内周表面上以便保持卷芯，第二活塞通过独立于第一流动路径的第二流动路径被压靠在保持器的端面上， 并且通过第二活塞和保持器之间的摩擦将卷绕轴的扭矩传递到保持器，滑块，芯片和卷绕芯，以使卷绕芯旋转。

公开(公告)号：US06864695B2

公开(公告)日：2005-03-08

申请号：US09925375

申请日：2001-08-10

申请人： Ryuji Kohno ,  Hideo Miura ,  Masatoshi Kanamaru ,  Hiroya Shimizu ,  Naoto Ban

发明人： Ryuji Kohno ,  Hideo Miura ,  Masatoshi Kanamaru ,  Hiroya Shimizu ,  Naoto Ban

IPC分类号： G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R3/00 ,  G01R1/07357

摘要： Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.

摘要翻译： 由于每个布线在波束的整个长度上以规定的宽度形成在相关联的光束的一个表面上，所以光束在沿着光束的任意纵向方向的任何点处具有在宽度方向上取下的截面形状。 结果，由光束和布线的形状确定的面积的第二时刻是均匀的。 这防止了当由于探针与被检体的垫接触而使光束弯曲预定量时局部变化的光束曲率的问题。 这反过来又防止梁中的局部应力集中，从而防止梁的断裂。 因此，能够将光束的强度保持在所要求的水平，能够使探头结构小型化，能够实现容纳多个探针的半导体装置的测试装置。

公开(公告)号：US06864568B2

公开(公告)日：2005-03-08

申请号：US10252546

申请日：2002-09-24

申请人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

发明人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  H01L21/66 ,  H01L23/02

CPC分类号： G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

摘要翻译： 一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置 半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件 并且延伸到包装装置的外部，使得探针连接到每个导电构件。

公开(公告)号：US20050029674A1

公开(公告)日：2005-02-10

申请号：US10919331

申请日：2004-08-17

申请人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

发明人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

摘要翻译： 多芯片模块具有至少两个半导体芯片。 每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层 土地和半导体芯片。 半导体芯片通过外部端子放置在安装板上。 第一半导体芯片的应力松弛层厚于第二半导体芯片的应力松弛层，该第二半导体芯片的距离其中心至位于其最外端部分的外部端子的距离小于第一半导体芯片的应力松弛层。

公开(公告)号：US20050006751A1

公开(公告)日：2005-01-13

申请号：US10909402

申请日：2004-08-03

申请人： Hiroya Shimizu ,  Asao Nishimura ,  Toshiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

发明人： Hiroya Shimizu ,  Asao Nishimura ,  Toshiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

IPC分类号： H01L21/3205 ,  H01L21/60 ,  H01L21/822 ,  H01L23/50 ,  H01L23/52 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L27/04 ,  H01L27/14

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.

摘要翻译： 一种半导体器件，包括具有第一电平的外部端子和高于第一电平的第二电平的外部电极的半导体元件。 外部端子包括形成在半导体元件的主表面上的电源端子，接地端子和信号端子。 外部电极包括通过电源连接部分连接到电源端子的电力电极，经由接地连接部分连接到接地端子的接地电极和经由信号连接部分连接到信号端子的信号电极。 信号端子，信号电极和相应的信号连接部分之一被连接电源端子和电源电极的电源连接部分或连接接地端子和接地电极的接地连接部分包围。

公开(公告)号：US06620704B2

公开(公告)日：2003-09-16

申请号：US09893980

申请日：2001-06-29

申请人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

发明人： Hideo Miura ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

IPC分类号： H01L2176

CPC分类号： H01L21/76205 ,  H01L21/76202 ,  H01L27/0802

摘要： A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

摘要翻译： 提供一种制造半导体器件的方法，该半导体器件包括在半导体衬底上形成氧化硅膜。 可以在氧化硅膜上形成亚硝酸硅膜。 可以在期望的部分去除一部分亚硝酸硅膜和氧化硅膜。 此外，可以在除去氧化硅膜的部分中的半导体衬底中形成沟槽。 氧化硅膜的一部分可以在硅亚硝酸盐膜位于上方的部分用氢氟酸型蚀刻回到槽周围。 此外，可以在半导体衬底的沟槽中形成氧化膜，并且可以使沟槽被氧化。

公开(公告)号：US06614246B1

公开(公告)日：2003-09-02

申请号：US09648452

申请日：2000-08-28

申请人： Ryuji Kohno ,  Tatsuya Nagata ,  Hiroya Shimizu ,  Toshio Miyatake ,  Hideo Miura

发明人： Ryuji Kohno ,  Tatsuya Nagata ,  Hiroya Shimizu ,  Toshio Miyatake ,  Hideo Miura

IPC分类号： G01R1073

CPC分类号： G01R1/07378

摘要： The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.

摘要翻译： 本发明提供了一种探针结构，其中形成探针的主要基底材料的二次电极即使在大面积形成大量探针的情况下也可以与衬底侧的电极电连接，从而使大量的LSIs 可以在晶片测试过程中一次性地测试晶片，从而可以提高测试过程的效率。 在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极 在基板侧经由插入件。

公开(公告)号：US06559037B2

公开(公告)日：2003-05-06

申请号：US09809046

申请日：2001-03-16

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US06476492B2

公开(公告)日：2002-11-05

申请号：US09758288

申请日：2001-01-12

申请人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

发明人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

IPC分类号： H01L2348

CPC分类号： H01L23/53257 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.

摘要翻译： 在包括第一电极的电容器组件，具有高介电常数或与第一电极接触的铁电性的氧化膜和与该氧化物膜接触的第二电极的电容器组件中， 在其上形成有金属布线层的硅衬底的主面上，通过使用含钼钨作为材料，可以解决半导体器件的钨互连断裂，可靠性降低，成品率降低等问题 金属互连层。