公开(公告)号：US10157888B1

公开(公告)日：2018-12-18

申请号：US15627458

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Tsung-Fu Tsai ,  Chen-Hua Yu ,  Po-Hao Tsai ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Hung-Wei Tsai ,  Chen-Hsuan Tsai

IPC: H01L21/68 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/66 ,  H01L25/10 ,  H01L21/683

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

公开(公告)号：US10103125B2

公开(公告)日：2018-10-16

申请号：US15362690

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Po-Hao Tsai ,  An-Jhih Su

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/60

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.

公开(公告)号：US09929050B2

公开(公告)日：2018-03-27

申请号：US13943245

申请日：2013-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/06

CPC classification number: H01L21/76898 ,  H01L21/76849 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

公开(公告)号：US20170352626A1

公开(公告)日：2017-12-07

申请号：US15175696

申请日：2016-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

公开(公告)号：US09508664B1

公开(公告)日：2016-11-29

申请号：US14970962

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Szu-Wei Lu ,  Yen-Yao Chi

IPC: H01L33/00 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/02 ,  H01L23/528 ,  H01L23/31 ,  H01L33/62

CPC classification number: H01L23/562 ,  H01L21/02068 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/32051 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L33/62 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/0541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的导电结构。 半导体器件结构包括导电结构上的第一金属氧化物纤维。 半导体器件结构包括在衬底上的电介质层并覆盖导电结构和第一金属氧化物纤维。 电介质层填充第一金属氧化物纤维之间的间隙。

公开(公告)号：US20160086918A1

公开(公告)日：2016-03-24

申请号：US14959094

申请日：2015-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6006 ,  H01L2021/6024 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05541 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.

Abstract translation: 提供一种半导体封装以及通过中介层形成具有一个或多个管芯的半导体封装的方法。 在一些实施例中，通过将具有一个或多个贯穿衬底通孔（TSV）的插入件放置在覆盖在第一载体衬底上的第一粘合剂层上来执行该方法。 连接结构沿着面向第一粘合剂层的中介层的第一表面布置。 在第一粘合剂层上形成第一模塑料并围绕插入件。 第一模塑料被布置成沿着插入件的第二表面暴露TSV。 第一再分配结构形成在插入件的第二表面和第一模塑料上，并且在第一再分配结构上形成导电凸块结构。 第一封装管芯结合到导电凸块结构。

公开(公告)号：US09252065B2

公开(公告)日：2016-02-02

申请号：US14087466

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4875 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/02 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with some embodiments, a package structure and a method for forming a package structure are provided. The package structure includes a semiconductor die and a molding compound partially or completely encapsulating the semiconductor die. The package structure also includes a through package via in the molding compound. The package structure further includes an interfacial layer between the through package via and the molding compound. The interfacial layer includes an insulating material and is in direct contact with the molding compound.

Abstract translation: 根据一些实施例，提供了一种用于形成封装结构的封装结构和方法。 封装结构包括半导体管芯和部分地或完全地封装半导体管芯的模塑料。 封装结构还包括在模塑料中的通孔封装通孔。 封装结构还包括通孔封装通孔和模塑料之间的界面层。 界面层包括绝缘材料并与模塑料直接接触。

公开(公告)号：US12249581B2

公开(公告)日：2025-03-11

申请号：US18521711

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

公开(公告)号：US12237291B2

公开(公告)日：2025-02-25

申请号：US17843725

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

公开(公告)号：US20240387393A1

公开(公告)日：2024-11-21

申请号：US18786966

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.