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公开(公告)号：US09793243B2
公开(公告)日：2017-10-17
申请号：US14459144
申请日：2014-08-13
发明人： Chen-Fa Lu , Cheng-Yuan Tsai , Yeur-Luen Tu , Chia-Shiung Tsai
IPC分类号： H01L23/498 , H01L23/31 , H01L23/58 , H01L25/065 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/00 , H01L25/00 , H01L27/06 , H01L21/822 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/76805 , H01L21/76877 , H01L21/76898 , H01L21/8221 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/80 , H01L24/89 , H01L25/50 , H01L27/0688 , H01L2224/023 , H01L2224/02351 , H01L2224/024 , H01L2224/0345 , H01L2224/0401 , H01L2224/05008 , H01L2224/05024 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/08145 , H01L2224/08146 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/12105 , H01L2224/13024 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2225/06548 , H01L2224/03 , H01L2224/11 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82 , H01L2924/01074
摘要： A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
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公开(公告)号：US20170294363A1
公开(公告)日：2017-10-12
申请号：US15626661
申请日：2017-06-19
发明人： Yao-Wen Chang , Cheng-Yuan Tsai , Kai-Wen Cheng
IPC分类号： H01L23/26 , H01L21/02 , H01L29/66 , H01L21/768 , H01L23/522 , H01L29/792
CPC分类号： H01L23/26 , H01L21/02186 , H01L21/28282 , H01L21/76868 , H01L21/76877 , H01L23/5226 , H01L29/4234
摘要： A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a conductive layer over the substrate such that the conductive layer is electrically coupled to the semiconductor device feature, forming a getter layer over the conductive layer, wherein the getter layer includes a first layer that is formed of titanium and a second layer overlying the first layer that is formed of tantalum nitride, and forming an interconnect layer over the getter layer such that the interconnect layer is electrically coupled to the semiconductor device feature.
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83.发明申请公开(公告)号：US20170229346A1
公开(公告)日：2017-08-10
申请号：US15170390
申请日：2016-06-01
IPC分类号： H01L21/78 , H01L21/02 , H01L23/00 , H01L21/768 , H01L23/29 , H01L23/31 , H01L21/683 , H01L21/3105
CPC分类号： H01L21/78 , H01L21/02178 , H01L21/0228 , H01L21/31053 , H01L21/6835 , H01L21/76895 , H01L23/291 , H01L23/3171 , H01L24/03 , H01L24/06 , H01L2221/68327 , H01L2924/05432 , H01L2924/14
摘要： Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.
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公开(公告)号：US20160204020A1
公开(公告)日：2016-07-14
申请号：US14592788
申请日：2015-01-08
发明人： Chih-Hui Huang , Yen-Chang Chu , Kuan-Liang Liu , Ping-Yin Liu , Cheng-Yuan Tsai , Yeur-Luen Tu , Chia-Shiung Tsai , Ru-Liang Lee
IPC分类号： H01L21/687 , H01L21/683 , H01L21/67
CPC分类号： H01L21/68785 , B32B37/1018 , B32B2457/14 , H01L21/67092 , H01L21/68 , H01L21/6838 , H01L21/68735 , H01L24/75 , H01L2224/757 , H01L2224/75983
摘要： A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.
摘要翻译： 讨论了使用粘合卡盘和包括粘合卡盘的工具的方法的粘合卡盘。 一种方法包括将第一晶片装载在第一接合卡盘的第一表面上，将第二晶片装载在第二接合卡盘上，以及将第一晶片接合到第二晶片。 第一表面至少部分地由第一球形表面的第一部分和第二球形表面的第二部分限定。 第一球面具有第一半径，第二球面具有第二半径。 第一个半径小于第二个半径。
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公开(公告)号：US20160155642A1
公开(公告)日：2016-06-02
申请号：US15016999
申请日：2016-02-05
发明人： Yao-Wen Chang , Cheng-Yuan Tsai , Hsing-Lien Lin
IPC分类号： H01L21/28 , H01L21/02 , H01L29/51 , H01L29/423 , H01L29/36 , H01L29/205 , H01L29/66 , H01L21/306
CPC分类号： H01L29/792 , C23C16/405 , C23C16/45525 , H01L21/02107 , H01L21/02109 , H01L21/02112 , H01L21/02175 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/0228 , H01L21/28158 , H01L21/28176 , H01L21/28264 , H01L21/30604 , H01L21/30612 , H01L23/485 , H01L27/10808 , H01L27/10852 , H01L27/10855 , H01L28/40 , H01L28/60 , H01L29/20 , H01L29/205 , H01L29/365 , H01L29/4236 , H01L29/517 , H01L29/66431 , H01L29/66462 , H01L29/66522 , H01L29/6656 , H01L29/7783 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.
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公开(公告)号：US20130307045A1
公开(公告)日：2013-11-21
申请号：US13948998
申请日：2013-07-23
发明人： Chih-Wei Lin , Yi-Fang Lee , Cheng-Ta Wu , Cheng-Yuan Tsai
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.
摘要翻译： 描述了非易失性存储器及其制造方法。 在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成氧化物层，并将氧化物层暴露于第一氮化步骤以形成第一富氮区域。 第一富氮区域设置在氧化物层和半导体衬底之间的界面附近。 在第一次氮化步骤之后，将氧化物层暴露于第二氮化步骤以形成第二富氮区域。 第一栅电极形成在氧化物层上，其中第二富氮区邻近氧化物层和第一栅电极之间的界面设置。
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公开(公告)号：US20240357835A1
公开(公告)日：2024-10-24
申请号：US18760266
申请日：2024-07-01
发明人： Hai-Dang Trinh , Yi Yang Wei , Bi-Shen Lee , Fa-Shen Jiang , Hsun-Chung Kuang , Cheng-Yuan Tsai
IPC分类号： H10B53/30
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first interconnect dielectric layer over a substrate and surrounding a first interconnect. A second interconnect dielectric layer is over the first interconnect dielectric layer and surrounds at least a part of a second interconnect. A bottom electrode is over the substrate, a top electrode is over the bottom electrode, and a ferroelectric layer is between the bottom electrode and the top electrode. The ferroelectric layer includes a lower horizontally extending portion, an upper horizontally extending portion arranged above the lower horizontally extending portion, and a vertically extending portion coupling the lower horizontally extending portion and the upper horizontally extending portion. The vertically extending portion extends through the first interconnect dielectric layer and the second interconnect dielectric layer.
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公开(公告)号：US12125763B2
公开(公告)日：2024-10-22
申请号：US18331249
申请日：2023-06-08
IPC分类号： H01L23/48 , H01L21/56 , H01L21/768 , H01L23/31 , H01L23/528 , H01L25/065
CPC分类号： H01L23/3185 , H01L21/56 , H01L21/76829 , H01L23/481 , H01L23/5283 , H01L25/0657
摘要： The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.
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公开(公告)号：US12080738B2
公开(公告)日：2024-09-03
申请号：US17400647
申请日：2021-08-12
发明人： Chih-Yu Lai , Min-Ying Tsai , Yeur-Luen Tu , Hai-Dang Trinh , Cheng-Yuan Tsai
IPC分类号： H01L27/146
CPC分类号： H01L27/1462 , H01L27/1463 , H01L27/1464 , H01L27/14654 , H01L27/14685 , H01L27/14627 , H01L27/14636 , H01L27/14689
摘要： An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
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公开(公告)号：US11862515B2
公开(公告)日：2024-01-02
申请号：US17880787
申请日：2022-08-04
IPC分类号： H01L21/00 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/528 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： H01L21/76834 , H01L21/76822 , H01L23/481 , H01L23/528 , H01L23/5226 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/80986
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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