公开(公告)号：US08232144B2

公开(公告)日：2012-07-31

申请号：US12560640

申请日：2009-09-16

申请人： Bernhard P Lange ,  Anthony L Coyle ,  Jeffrey G Holloway

发明人： Bernhard P Lange ,  Anthony L Coyle ,  Jeffrey G Holloway

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

摘要翻译： 本文公开了一种制造半导体封装的方法，该半导体封装在引线焊盘上具有焊接位置，该焊盘抵达封装的边缘（非拉回引线）。 它包括将多个管芯封装在引线框架条上。 引线框架条包括多个封装位置，其还包括多个引线焊盘和管芯焊盘。 该方法还包括在附近的封装位置的引线焊盘之间形成通道，而不需要对封装进行分离。 该方法的另一步骤包括在焊盘，芯片焊盘或引线焊盘和裸片焊盘上布置焊料，而基本上不用焊料覆盖焊道。 制造方法还包括将包装分离。

公开(公告)号：US08053876B2

公开(公告)日：2011-11-08

申请号：US12573196

申请日：2009-10-05

申请人： Steven A Kummerl ,  Bernhard P Lange ,  Anthony L Coyle

发明人： Steven A Kummerl ,  Bernhard P Lange ,  Anthony L Coyle

IPC分类号： H01L23/495 ,  H01L21/00 ,  H05K7/20

CPC分类号： H01L23/4334 ,  H01L23/49537 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P1/387 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates thermal energy. The first lead frame is disposed at least partially within the mold compound and is operable to facilitate transmission of a signal. The second lead frame is disposed at least partially within the compound, at least partially separated from the first lead frame, and is operable to facilitate a dissipation of thermal energy.

摘要翻译： 根据本发明的实施例，可操作以便于散热的能量的系统包括模具化合物，模具，第一引线框架和第二引线框架。 模具设置在模具化合物内，并且在操作中产生热能。 第一引线框架至少部分地设置在模具化合物内，并且可操作以促进信号的传输。 第二引线框架至少部分地设置在化合物内，至少部分地与第一引线框架分离，并且可操作以便于散热热能。

公开(公告)号：US20100164052A1

公开(公告)日：2010-07-01

申请号：US12347522

申请日：2008-12-31

申请人： STEFAN W. WIKTOR ,  VLADIMIR A. MURATOV ,  ANTHONY L. COYLE ,  BERNHARD P. LANGE

发明人： STEFAN W. WIKTOR ,  VLADIMIR A. MURATOV ,  ANTHONY L. COYLE ,  BERNHARD P. LANGE

IPC分类号： H01L29/72 ,  H01L23/485

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.

摘要翻译： 集成电路（IC）包括具有半导体表面的衬底，在半导体表面上和半导体表面中的第一阵列的器件，包括第一和第二共同电流导电节点，多个层，设置在衬底上并且包括导电层和 电介质层，以及介电层顶表面上或其中的多个凸块焊盘。 在IC中，导电层限定电迹线，其中电迹线的第一部分将凸点焊盘的第一部分独占地与第一共同电流传导节点的一部分接触，其中电迹线的第二部分接触 凸块的第二部分专用于第二共同电流传导节点的一部分，并且其中电迹线通过电介质层彼此电隔离。

公开(公告)号：US20080135990A1

公开(公告)日：2008-06-12

申请号：US11567839

申请日：2006-12-07

申请人： Anthony L. Coyle ,  Jie-Hua Zhao

发明人： Anthony L. Coyle ,  Jie-Hua Zhao

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L21/4828 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device (100) with a metal bump (203) on each interior contact pad (202) has a metallic leadframe with lead segments (220) with the first surface (220a) in one plane. The second surface (220b) is castellated across the segment width in two planes so that regions of a first segment thickness (240a) alternate with regions of a reduced (about 50%) second segment thickness (240b); the first thickness regions are in the locations corresponding to the chip interior contact pads (half-etched leadframe). The second segment surface faces the chip so that each first thickness region aligns with the corresponding chip bump. The chip bumps are attached to the corresponding second segment surface using reflow metal. Dependent on the orientation of the attached half-etched segment, thermomechanical stress concentrations away shift from the solder joints into the leadframe metal, or shear stress may reduced.

摘要翻译： 在每个内部接触焊盘（202）上具有金属凸块（203）的半导体器件（100）具有金属引线框架，其具有在一个平面中的第一表面（220a）的引线段（220）。 所述第二表面（220b）在两个平面中跨越所述段宽度被浇注，使得第一段厚度（240a）的区域与减小的（约50％）第二段厚度（240b）的区域交替; 第一厚度区域位于对应于芯片内部接触焊盘（半蚀刻引线框架）的位置。 第二段表面面向芯片，使得每个第一厚度区域与相应的芯片凸块对准。 使用回流金属将芯片凸块附接到相应的第二段表面。 取决于连接的半蚀刻段的取向，从焊接点移动到引线框架金属中的热机械应力集中或剪切应力可能降低。

公开(公告)号：US07256482B2

公开(公告)日：2007-08-14

申请号：US10917036

申请日：2004-08-12

申请人： Steven Alfred Kummerl ,  Anthony L. Coyle ,  Bernhard Lange

发明人： Steven Alfred Kummerl ,  Anthony L. Coyle ,  Bernhard Lange

IPC分类号： H01L23/495 ,  H01L23/28 ,  H01L23/48

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.

摘要翻译： 一种具有第一和第二封装侧的集成电路芯片封装组件。 集成电路芯片具有基板侧和有源电路侧。 芯片包括形成在有源电路侧的集成电路器件。 芯片的有源电路侧位于第一封装侧。 模片垫具有从其延伸的至少一个浇道构件，其可以朝着第一封装侧弯曲。 芯片的有源电路侧连接到管芯焊盘。 芯片焊盘相对于芯片在第一封装侧。 封装模具化合物形成在芯片焊盘，芯片的至少一部分和流道部件的至少一部分之上。 芯片的基板侧的至少一部分和/或流道部件的至少一部分可以不被封装模具化合物覆盖。

公开(公告)号：US06916689B2

公开(公告)日：2005-07-12

申请号：US10419408

申请日：2003-04-21

申请人： Samuel D. Pritchett ,  Anthony L. Coyle ,  Milton L. Buschbom

发明人： Samuel D. Pritchett ,  Anthony L. Coyle ,  Milton L. Buschbom

IPC分类号： H01L25/18 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L25/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.

摘要翻译： 半导体器件具有与电路集成的无源元件，并封装在用于焊球或引线附件的塑料封装中。 塑料芯片级半导体器件具有由多个图案化的绝缘层与图案化的导电层交替的衬底，所述层相互粘附以形成衬底。 这些层包括多个无源电部件，例如电容器，电感器和电阻器以及布线线。 大多数路由线终止于第一多个可结合接触焊盘和第二多个可焊接接触焊盘中。 部件和线形成网状物，并且至少部分地围绕中心基板区域大部分地配置在窄的外围带中，并且与集成电路（IC）芯片结合可高性能地操作。 芯片附接到中央基板区域并分别电连接到第一多个接触焊盘，由此无源部件与IC集成。 塑料封装材料围绕芯片，第一多个接触焊盘和无源部件，使得材料的轮廓与芯片的轮廓大致相同。

公开(公告)号：US06586676B2

公开(公告)日：2003-07-01

申请号：US09855879

申请日：2001-05-15

申请人： Samuel D. Pritchett ,  Anthony L. Coyle ,  Milton L. Buschbom

发明人： Samuel D. Pritchett ,  Anthony L. Coyle ,  Milton L. Buschbom

IPC分类号： H01L2328

CPC分类号： H01L25/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.

摘要翻译： 半导体器件具有与电路集成的无源元件，并封装在用于焊球或引线附件的塑料封装中。 塑料芯片级半导体器件具有由多个图案化的绝缘层与图案化的导电层交替的衬底，所述层相互粘附以形成衬底。 这些层包括多个无源电部件，例如电容器，电感器和电阻器以及布线线。 大多数路由线终止于第一多个可结合接触焊盘和第二多个可焊接接触焊盘中。 部件和线形成网状物，并且至少部分地围绕中心基板区域大部分地配置在窄的外围带中，并且与集成电路（IC）芯片结合可高性能地操作。 芯片附接到中央基板区域并分别电连接到第一多个接触焊盘，由此无源部件与IC集成。 塑料封装材料围绕芯片，第一多个接触焊盘和无源部件，使得材料的轮廓与芯片的轮廓大致相同。

公开(公告)号：US06489178B2

公开(公告)日：2002-12-03

申请号：US09766195

申请日：2001-01-19

申请人： Anthony L. Coyle ,  George A. Bednarz

发明人： Anthony L. Coyle ,  George A. Bednarz

IPC分类号： H01L2100

CPC分类号： B81C1/00333 ,  B29C45/14655 ,  B29C2045/14663 ,  B81C2203/0154 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/05599 ,  H01L2924/01004 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

摘要： A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

摘要翻译： 用于微机械部件的塑料格栅阵列封装，球栅阵列封装和塑料引线封装通过模制工艺制造，其特征在于用保护性塑料膜对顶部和底部半模的空腔表面进行衬里，其也是 在模制阶段期间保护部件的表面，选择性地封装芯片的焊盘和耦合部件，同时在部件之上留下空的空间，以及在组件上安装盖子。 提供了与微机械装置的灵敏度兼容的成型方法以及模制装置，但是对于用于组装芯片和基板的技术而言，它是灵活的。 此外，所公开的方法对于基材的材料和性质是柔性的。 本发明的一个方面可应用于各种不同的半导体微机械装置，例如致动器，马达，传感器，空间光调制器和可变形反射镜装置。 在所有应用中，本发明实现了技术优点以及显着的成本降低和产量增加。

公开(公告)号：US07476976B2

公开(公告)日：2009-01-13

申请号：US11358668

申请日：2006-02-21

申请人： Bernhard P. Lange ,  Anthony L. Coyle

发明人： Bernhard P. Lange ,  Anthony L. Coyle

IPC分类号： H01L23/52 ,  H01L23/34

CPC分类号： H01L23/4334 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/2076 ,  H01L2924/20754 ,  H01L2924/00012 ,  H01L2224/05099

摘要： A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip.

摘要翻译： 提供了一种QFN封装及其制造方法，包括：具有从衬底的周边区域上的连接元件延伸到衬底的内部区域上的高电流接触焊盘的金属线的衬底。 具有活性表面的半导体芯片大致面向衬底的内部区域，其中散热图案化的金属分布层形成在活性表面上并与其上的活性组分电连接。 焊接电极电连接高电流接触焊盘和金属分布层，并且模制化合物通常封装半导体芯片。 焊料条的深度和表面积通常是均匀的，其中在高电流接触焊盘和金属分布层之间提供低电阻和电感。 集成散热器可以进一步形成或放置在芯片的被动表面上。

公开(公告)号：US20070296056A1

公开(公告)日：2007-12-27

申请号：US11426591

申请日：2006-06-27

申请人： Anthony L. Coyle ,  Reynaldo C. Javier ,  Jeffrey G. Holloway

发明人： Anthony L. Coyle ,  Reynaldo C. Javier ,  Jeffrey G. Holloway

IPC分类号： H01L29/00

CPC分类号： H01L24/85 ,  H01F17/0006 ,  H01F17/02 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/4813 ,  H01L2224/48599 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/00014

摘要： An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance of the wire; the inductance is selected to fine-tune the high frequency characteristics of the circuit.

摘要翻译： 电子设备具有表面和包括端子在内的电路的半导体芯片（101）。 电路具有用于引线接合的冶金组合物的第一（103）和第二端子（104）。 芯片具有在芯片表面上方的导线（120），其具有长度和第一和第二端; 第一端附接到第一端子，第二端部连接到第二端子。 导线成形为形成至少一个凹部和凸部的序列。 该顺序可以被配置为形成环路，或者多个线环形成螺旋线圈。 回路的数量，形状和空间顺序控制电线的电感; 选择电感来微调电路的高频特性。