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18 条记录 (耗时 0.026 秒)

    DEVICE PERFORMANCE IMPROVEMENT USING BACKSIDE METALLIZATION IN A LAYER TRANSFER PROCESS
    1.
    发明申请
    DEVICE PERFORMANCE IMPROVEMENT USING BACKSIDE METALLIZATION IN A LAYER TRANSFER PROCESS 审中-公开

    公开(公告)号：US20180061763A1

    公开(公告)日：2018-03-01

    申请号：US15246453

    申请日：2016-08-24

    申请人： Qualcomm Switch Corp.

    发明人： Sinan GOKTEPELI

    IPC分类号： H01L23/535 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L27/12 ,  H03K17/687

    摘要： A silicon-on-insulator (SOI) device includes an active layer including active, devices, such as transistors. Below the active layer is an insulating layer, e.g., an SOI buried oxide layer (BOX), and below the BOX layer, one or more metal layers. The metal layer adjacent the BOX layer includes at least one metal region positioned below a corresponding active device, e.g., the channel region or diffusion region of the transistor. The metal region, during operation of the device, may act as a heat sink for the active device or may be biased to improve the performance of the active device.

    Integrated Circuit Assembly and Method of Making
    2.
    发明申请
    Integrated Circuit Assembly and Method of Making 审中-公开
    集成电路组装及制作方法

    公开(公告)号：US20160284671A1

    公开(公告)日：2016-09-29

    申请号：US15173251

    申请日：2016-06-03

    申请人： QUALCOMM SWITCH CORP.

    发明人： Michael A. Stuber ,  Stuart B. Molin ,  Mark Drucker ,  Peter Fowler

    IPC分类号： H01L25/065 ,  H01L27/12 ,  H01L23/00

    摘要： An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

    摘要翻译： 集成电路组件包括具有第一表面和第二表面的绝缘层。 第一有源层接触绝缘层的第一表面。 金属接合焊盘与第一有源层电连接并形成在绝缘层的第二表面上。 提供具有第一表面和第二表面的衬底，其中形成在第一表面中的第二有源层使得第一有源层耦合到衬底的第二表面。

    Charge pump regulator circuit
    6.
    发明授权
    Charge pump regulator circuit 有权
    电荷泵调节电路

    公开(公告)号：US09385595B2

    公开(公告)日：2016-07-05

    申请号：US14789745

    申请日：2015-07-01

    申请人： QUALCOMM SWITCH CORP.

    发明人： Stuart B. Molin ,  Perry Lou ,  Clint Kemerling

    IPC分类号： G05F1/10 ,  H02M3/07

    CPC分类号： H02M3/07 ,  G05F1/10

    摘要： A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a peak-to-peak amplitude that is variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

    摘要翻译： 电荷泵调节器电路包括振荡器和一个或多个电荷泵。 一个或多个振荡信号由振荡器产生。 每个振荡信号具有取决于可变驱动信号而变化的峰 - 峰幅度。 对于具有多个振荡信号的一些实施例，每个振荡信号从先前的振荡信号相移。 对于具有多个电荷泵的一些实施例，每个电荷泵连接以接收相应的一个振荡信号。 每个电荷泵输出电压和电流。 对于具有多个电荷泵的一些实施例，每个电荷泵的输出从其它电荷泵的输出相移。 这样产生的电流的组合提供在大约与负载的电压电平上。

    LOW POWER EXTERNALLY BIASED POWER-ON-RESET CIRCUIT
    7.
    发明申请
    LOW POWER EXTERNALLY BIASED POWER-ON-RESET CIRCUIT 有权
    低功耗外部偏置上电复位电路

    公开(公告)号：US20160105169A1

    公开(公告)日：2016-04-14

    申请号：US14510989

    申请日：2014-10-09

    申请人： QUALCOMM SWITCH CORP.

    发明人： Perry Lou

    IPC分类号： H03K17/22

    CPC分类号： H03K17/223 ,  H03K2217/0036

    摘要： Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply voltage has reached a desired level comprises a sense circuit and a delayed buffer. The sense circuit comprises: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level. The delayed buffer is coupled to the output node of the sense circuit that generates the POR signal in response to the voltage transition. The feedback circuit shuts off the sense circuit in response to the voltage transition. The POR circuit generates the POR signal for a local system. The known bias voltage is provided by an external system.

    摘要翻译： 本文公开了涉及上电复位（POR）电路的各种方法和装置。 用于在检测到电源电压达到期望电平时产生POR信号的示例性POR电路包括检测电路和延迟缓冲器。 感测电路包括：（i）由已知偏置电压供电的逆变器; （ii）由电源电压供电的反馈电路; 和（iii）感测电路的输出节点，当电源电压达到期望的水平时，该输出节点经历电压转换。 延迟缓冲器耦合到感测电路的输出节点，其响应于电压转换而产生POR信号。 反馈电路响应于电压转换而关闭感测电路。 POR电路为本地系统生成POR信号。 已知的偏置电压由外部系统提供。

    Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
    9.
    发明授权
    Semiconductor-on-insulator integrated circuit with reduced off-state capacitance 有权
    具有降低截止电容的绝缘体上半导体集成电路

    公开(公告)号：US09331098B2

    公开(公告)日：2016-05-03

    申请号：US14335906

    申请日：2014-07-19

    申请人： QUALCOMM SWITCH CORP.

    发明人： Michael A. Stuber ,  Stuart B. Molin ,  Chris Brindle

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/12 ,  H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.

    摘要翻译： 集成电路组件包括绝缘层，半导体层，手柄层，金属互连层和晶体管。 绝缘层具有第一表面，第二表面和从第一表面延伸到第二表面的孔。 半导体层具有第一表面和第二表面，半导体层的第一表面与绝缘层的第一表面接触。 手柄层耦合到半导体层的第二表面。 金属互连层耦合到绝缘层的第二表面，金属互连层设置在绝缘层中的孔内。 晶体管位于半导体层中。 绝缘层中的孔至少延伸到半导体层的第一表面。 金属互连层将多个晶体管彼此电耦合。

    Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop
    10.
    发明授权
    Bonded semiconductor structure with SiGeC/SiGeBC layer as etch stop 有权
    具有SiGeC / SiGeBC层的结合半导体结构作为蚀刻停止

    公开(公告)号：US09269608B2

    公开(公告)日：2016-02-23

    申请号：US14673309

    申请日：2015-03-30

    申请人： QUALCOMM SWITCH CORP.

    发明人： Stephen A. Fanelli

    IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/762 ,  H01L29/78

    CPC分类号： H01L21/76256 ,  H01L29/7849

    摘要： A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC or SiGeBC layer as an etch stop. In some embodiments, the SiGeC or SiGeBC layer is formed by epitaxial growth, ion implantation or a combination of epitaxial growth and ion implantation.

    摘要翻译： 半导体结构形成有第一晶片（例如，手柄晶片）和第二晶片（例如，体硅晶片）结合在一起。 第二晶片包括有源层，其在一些实施例中在两个晶片接合在一起之前形成。 使用SiGeC或SiGeBC层作为蚀刻停止层，从有源层的与第一晶片相反的一侧的第二晶片上去除衬底。 在一些实施例中，通过外延生长，离子注入或外延生长和离子注入的组合来形成SiGeC或SiGeBC层。