公开(公告)号：US06323045B1

公开(公告)日：2001-11-27

申请号：US09456590

申请日：1999-12-08

申请人： Christopher Cline ,  Nancy W. Hannon ,  Chandrika Prasad ,  Thomas A. Wassick ,  Roy Yu

发明人： Christopher Cline ,  Nancy W. Hannon ,  Chandrika Prasad ,  Thomas A. Wassick ,  Roy Yu

IPC分类号： G01R3126

CPC分类号： H05K3/225 ,  H01L21/485 ,  H01L23/5382 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for providing top-to-bottom repair of a defective I/O net in a thin film transfer and join process. At least one C4 location and at least one capture pad are provided on a thin film substrate. The substrate is preferably ceramic. The C4 location of the defective net is severed by removal of a delete strap. The corresponding solder connection of the associated capture pad is also removed. A spare C4 location and capture pad are connected to provide a Z-repair line imbedded in the TF wiring structure. The Z-repair line is wired to the defective net.

摘要翻译： 一种用于在薄膜转移和连接过程中提供缺陷I / O网络的从顶部到底部修复的方法和结构。 至少一个C4位置和至少一个捕获垫设置在薄膜基板上。 基材优选为陶瓷。 有缺陷的网的C4位置通过删除删除带被切断。 相关联的捕获垫的相应焊接连接也被去除。 连接备用C4位置和捕获垫以提供嵌入在TF布线结构中的Z维修线。 Z维修线路连接到有缺陷的网络。

公开(公告)号：US06856025B2

公开(公告)日：2005-02-15

申请号：US10465506

申请日：2003-06-19

申请人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

发明人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC分类号： H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

摘要翻译： 描述了在芯片级或晶片级的半导体器件集成的过程，其中通过衬底形成垂直连接。 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。

公开(公告)号：US06737297B2

公开(公告)日：2004-05-18

申请号：US10213872

申请日：2002-08-06

申请人： H. Bernhard Pogge ,  Chandrika Prasad ,  Roy Yu

发明人： H. Bernhard Pogge ,  Chandrika Prasad ,  Roy Yu

IPC分类号： H01L2144

CPC分类号： H01L21/6835 ,  H01L23/5389 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2224/0401

摘要： A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

摘要翻译： 使用螺柱/通孔匹配结构制造包括芯片之间的细间距连接的半导体器件结构。 螺柱和通孔对准和连接，从而允许细间距芯片放置和电互连。 然后将芯片支撑件附接到该装置。 临时芯片对准结构包括暴露于消融辐射的透明板; 然后将板拆下并取出。 该方法允许在紧密接近且具有非常高的布线密度的情况下互连多个芯片（通常具有不同尺寸，架构和功能）。 该设备可以包括位于分离的芯片上的无源组件，使得该设备包括具有和不具有有源设备的芯片。

公开(公告)号：US6099935A

公开(公告)日：2000-08-08

申请号：US573469

申请日：1995-12-15

申请人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

发明人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

IPC分类号： H01L21/60 ,  H01L21/68 ,  H05K3/34 ,  B23K31/02

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L24/75 ,  H05K3/3484 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/11003 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11472 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  Y10T428/24174 ,  Y10T428/24273 ,  Y10T428/24479

摘要： An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.

摘要翻译： 一种用于制造半导体器件的装置，其具有以IO阵列布置在IO面上的输入 - 输出（IO）焊盘，该主体具有从操作面延伸到主体中的多个空腔; 空腔被布置在空腔轨迹阵列中，当该设备处于制造位置时，其中操作面大体上邻近IO面，该腔轨迹阵列与IO凸台对齐。 每个空腔具有深度和横向宽度，其协作以建立由空腔底部和至少一个空腔壁限定的体积。 当装置处于制造位置时，体积容纳适当量的焊料材料以建立在面对的IO焊盘上的焊料材料的量度。 当装置处于制造位置时，该深度适于促进将焊料材料润湿地吸引到相对的IO焊盘，并且半导体器件和设备暴露于适当的环境条件以实现焊料材料的回流。 本发明还包括一种在制造半导体器件中使用该装置的方法。

公开(公告)号：US6090633A

公开(公告)日：2000-07-18

申请号：US401098

申请日：1999-09-22

申请人： Roy Yu ,  Chandrika Prasad ,  John R. Pennacchia ,  Harvey C. Hamel

发明人： Roy Yu ,  Chandrika Prasad ,  John R. Pennacchia ,  Harvey C. Hamel

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/40 ,  H05K3/46 ,  H01L23/02 ,  H01L23/053 ,  H01L23/12 ,  H01L29/40 ,  G01R21/66

CPC分类号： H05K3/462 ,  H01L21/485 ,  H01L23/5382 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K2201/0305 ,  H05K2203/016 ,  H05K2203/063 ,  H05K2203/162 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/467 ,  H05K3/4688

摘要： A multiple plane pair thin-film structure and a process for the manufacture of that structure. The multiple plane pair thin-film structure is of modular design and manufacture, such that each module comprising the structure is manufactured and tested individually before assembly. The thin film wiring structure is comprised of a plurality of true plane pair thin-film structures. Each such plane pair thin-film structure is manufactured as a module, the functionality of which can be tested for conformity to applicable specifications. Each module is designed and fabricated as a plane pair thin-film structure.

摘要翻译： 多平面对薄膜结构和制造该结构的方法。 多平面对薄膜结构具有模块化设计和制造，使得包括该结构的每个模块在组装之前单独制造和测试。 薄膜布线结构由多个真平面对薄膜结构构成。 每个这样的平面对薄膜结构被制造为模块，其功能可以被测试以符合适用的规范。 每个模块设计和制造为平面对薄膜结构。

公开(公告)号：US20070252287A1

公开(公告)日：2007-11-01

申请号：US11765465

申请日：2007-06-20

申请人： H. Pogge ,  Chandrika Prasad ,  Roy Yu

发明人： H. Pogge ,  Chandrika Prasad ,  Roy Yu

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83365 ,  H01L2224/83907 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599

摘要： A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

摘要翻译： 描述了一种用于形成集成结构的方法，包括半导体器件和用于连接到母板的连接器。 第一层形成在对消融辐射透明的板上，在半导体器件上形成第二层。 第一层具有连接到接合焊盘的第一组导体，该第一组导体根据与母板的连接的所需间隔而间隔开第一间隔距离。 第二层具有连接到半导体器件的第二组导体。 第一层和第二层使用间距小于接合焊盘的螺柱/通孔连接器连接。 因此，半导体器件被附接到第一层，并且第一组和第二组导体通过螺柱连接。 通过烧蚀透过板的辐射来消除第一层和板之间的界面，从而分离板。 然后将连接器结构附接到接合焊盘。 该方法允许以低成本制造高密度封装装置。

公开(公告)号：US20050121711A1

公开(公告)日：2005-06-09

申请号：US11033926

申请日：2005-01-12

申请人： H. Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

发明人： H. Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC分类号： H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：US20050056943A1

公开(公告)日：2005-03-17

申请号：US10709946

申请日：2004-06-08

申请人： H. Pogge ,  Chandrika Prasad ,  Roy Yu

发明人： H. Pogge ,  Chandrika Prasad ,  Roy Yu

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L23/24 ,  H01L23/498 ,  H01L23/12

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83365 ,  H01L2224/83907 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599

摘要： A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

摘要翻译： 描述了一种用于形成集成结构的方法，包括半导体器件和用于连接到母板的连接器。 第一层形成在对消融辐射透明的板上，在半导体器件上形成第二层。 第一层具有连接到接合焊盘的第一组导体，该第一组导体根据与母板的连接的所需间隔而间隔开第一间隔距离。 第二层具有连接到半导体器件的第二组导体。 第一层和第二层使用间距小于接合焊盘的螺柱/通孔连接器连接。 因此，半导体器件被附接到第一层，并且第一组和第二组导体通过螺栓连接。 通过烧蚀透过板的辐射来消除第一层和板之间的界面，从而分离板。 然后将连接器结构附接到接合焊盘。 该方法允许以低成本制造高密度封装装置。

公开(公告)号：US06669833B2

公开(公告)日：2003-12-30

申请号：US10405537

申请日：2003-04-02

申请人： Suryanarayana Kaja ,  Chandrika Prasad ,  RongQing Roy Yu

发明人： Suryanarayana Kaja ,  Chandrika Prasad ,  RongQing Roy Yu

IPC分类号： C25D500

CPC分类号： C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  C25D17/008 ,  H05K3/241 ,  Y10S204/07

摘要： A process and apparatus are provided for electroplating a film onto a substrate having a top side including a plating surface includes the following steps. Provide a plating tank with an electroplating bath. Provide an anode in the bath. Place a substrate having a plating surface to be electroplated into the electroplating bath connecting surfaces to be plated to a first cathode. Support a second cathode including a portion thereof with openings therethrough extending across the plating surface of the substrate and positioned between the substrate and the anode. Connect power to provide a negative voltage to the first cathode and provide a negative voltage to the second cathode, and provide a positive voltage to the anode.

摘要翻译： 提供了一种用于将膜电镀到具有包括电镀表面的顶侧的基板上的工艺和设备，包括以下步骤。 提供带电镀槽的电镀槽。 在浴缸里提供阳极。 将具有要电镀的电镀表面的衬底放置到要镀覆的电镀浴连接表面到第一阴极。 支撑包括其一部分的第二阴极，其开口穿过基板的电镀表面延伸并且定位在基板和阳极之间。 连接电源以向第一阴极提供负电压，并向第二阴极提供负电压，并向阳极提供正电压。

公开(公告)号：US20080230891A1

公开(公告)日：2008-09-25

申请号：US12114145

申请日：2008-05-02

申请人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

发明人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC分类号： H01L23/522

CPC分类号： H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

摘要翻译： 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。