公开(公告)号：US20210177026A1

公开(公告)日：2021-06-17

申请号：US16761811

申请日：2018-10-11

申请人： Ji Hwan HWANG ,  UNIVERSITY INDUSTRY FOUNDATION, YONSEI UNIVERSITY

发明人： Ji Hwan HWANG ,  Eun Jig LEE ,  Cheol Ryong KU

IPC分类号： A23L29/00

摘要： Disclosed is an enzyme composition for regulating sugar metabolism which can regulate the absorption of glucose into the body by converting the carbohydrates in food to a form of sugar that is not absorbed in the stomach and the like before being decomposed in the small intestine into glucose by the activity of various enzymes such as maltase, sucrase, or lactase and the like and absorbed, wherein the enzyme composition includes: one or more enzymes selected from the group consisting of glucoamylase, sucrase and lactase; glucose oxidase; and transglucosidase.

公开(公告)号：US20140117536A1

公开(公告)日：2014-05-01

申请号：US13693142

申请日：2012-12-04

申请人： Ji-Hwan HWANG ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

发明人： Ji-Hwan HWANG ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

IPC分类号： H05K1/02 ,  H01L23/00

CPC分类号： H05K1/0277 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/10128 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

摘要： A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.

摘要翻译： 布线基板包括基膜，多个第一布线和多个第二布线。 基膜具有芯片安装区域，用于在其上安装半导体芯片。 第一布线沿芯片安装区域内的第一方向延伸到芯片安装区域的外部，并且包括沿与第一方向不同的第二方向延伸的第一连接端部。 第一连接端部可以形成在芯片安装区域的内部并且被配置为电连接到半导体芯片。 所述第二配线从所述芯片安装区域的内部朝向所述芯片安装区域的外部沿所述第一方向延伸，并且包括沿与所述第一连接端部延伸的所述第二方向相反的方向延伸的第二连接端部， 连接端部可以形成在芯片安装区域内部，并且被配置为电连接到半导体芯片。

公开(公告)号：US08791562B2

公开(公告)日：2014-07-29

申请号：US13183645

申请日：2011-07-15

申请人： Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

发明人： Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

IPC分类号： H01L23/58 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

摘要翻译： 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US08742577B2

公开(公告)日：2014-06-03

申请号：US13550949

申请日：2012-07-17

申请人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

发明人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/05042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

摘要翻译： 半导体封装包括第一半导体芯片，设置在第一半导体芯片上的第二半导体芯片和用于电连接第一半导体芯片和第二半导体芯片的连接构件。 连接构件可以包括设置在第一半导体芯片上的连接焊盘，设置在第二半导体芯片上的连接柱和用于连接连接焊盘和连接柱的接合构件。 可以在连接焊盘的至少一个表面上形成抗接触层。

公开(公告)号：US20120018871A1

公开(公告)日：2012-01-26

申请号：US13183645

申请日：2011-07-15

申请人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

发明人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

IPC分类号： H01L23/58

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

摘要翻译： 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US20080119061A1

公开(公告)日：2008-05-22

申请号：US11758175

申请日：2007-06-05

申请人： Ji-hwan HWANG ,  Dong-han KIM ,  Chul-woo KIM ,  Sang-heui LEE ,  Kwang-jin BAE

发明人： Ji-hwan HWANG ,  Dong-han KIM ,  Chul-woo KIM ,  Sang-heui LEE ,  Kwang-jin BAE

IPC分类号： H01L23/48 ,  H05K1/00

CPC分类号： H01L23/49572 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/189 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor chip is disclosed and includes a plurality of bond pads disposed on a semiconductor chip, and a plurality of chip bumps of different heights disposed on a corresponding bond pad.

摘要翻译： 公开了一种半导体芯片，并且包括设置在半导体芯片上的多个接合焊盘以及设置在相应的焊盘上的不同高度的多个芯片凸块。

公开(公告)号：US08339561B2

公开(公告)日：2012-12-25

申请号：US12353317

申请日：2009-01-14

申请人： Ji-Hwan Hwang ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

发明人： Ji-Hwan Hwang ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

IPC分类号： G02F1/1345

CPC分类号： H05K1/0277 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/10128 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

摘要： A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.

摘要翻译： 布线基板包括基膜，多个第一布线和多个第二布线。 基膜具有芯片安装区域，用于在其上安装半导体芯片。 第一布线沿芯片安装区域内的第一方向延伸到芯片安装区域的外部，并且包括沿与第一方向不同的第二方向延伸的第一连接端部。 第一连接端部可以形成在芯片安装区域的内部并且被配置为电连接到半导体芯片。 所述第二配线从所述芯片安装区域的内部朝向所述芯片安装区域的外侧沿所述第一方向延伸，并且包括沿与所述第一连接端部延伸的所述第二方向相反的方向延伸的第二连接端部， 连接端部可以形成在芯片安装区域内部，并且被配置为电连接到半导体芯片。

公开(公告)号：US20160087004A1

公开(公告)日：2016-03-24

申请号：US14635920

申请日：2015-03-02

申请人： Yasuyuki SONODA ,  Min Suk LEE ,  Ji Hwan HWANG ,  Chang Hyup SHIN ,  Masatoshi YOSHIKAWA

发明人： Yasuyuki SONODA ,  Min Suk LEE ,  Ji Hwan HWANG ,  Chang Hyup SHIN ,  Masatoshi YOSHIKAWA

IPC分类号： H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L27/228 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory includes a magnetic element, and a metal layer stacked on the magnetic element. H/D>1.47 is satisfied, where H denotes a sum of thicknesses of the magnetic element and the metal layer in a first direction in which the magnetic element and the metal layer are stacked, and D denotes a width of the magnetic element in a second direction perpendicular to the first direction.

摘要翻译： 根据一个实施例，磁存储器包括磁性元件和堆叠在磁性元件上的金属层。 H / D> 1.47，其中H表示在磁性元件和金属层堆叠的第一方向上的磁性元件和金属层的厚度之和，D表示磁性元件和金属层的宽度 第二方向垂直于第一方向。

公开(公告)号：US20130087917A1

公开(公告)日：2013-04-11

申请号：US13550949

申请日：2012-07-17

申请人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

发明人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/05042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

摘要翻译： 半导体封装包括第一半导体芯片，设置在第一半导体芯片上的第二半导体芯片和用于电连接第一半导体芯片和第二半导体芯片的连接构件。 连接构件可以包括设置在第一半导体芯片上的连接焊盘，设置在第二半导体芯片上的连接柱和用于连接连接焊盘和连接柱的接合构件。 可以在连接焊盘的至少一个表面上形成抗接触层。

公开(公告)号：US20120223433A1

公开(公告)日：2012-09-06

申请号：US13409480

申请日：2012-03-01

申请人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

发明人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

IPC分类号： H01L23/488

CPC分类号： B23K35/262 ,  B23K35/3013 ,  B23K35/3033 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

摘要翻译： 一种半导体封装，其包括通过防止形成具有高脆度的金属间化合物而具有可控含量比的能够提高耐久性和可靠性的连接构件。 半导体封装包括基底; 设置在所述基底基板上的第一半导体芯片; 以及第一连接构件，用于电连接基底基板和第一半导体芯片，并且包括第一接合部分，其包括金并且具有被控制以防止AuSn4（Cu，Au）的金属间化合物的金的第一含量比， Sn4或（Ni，Au）Sn4的形成。