公开(公告)号：US20130127032A1

公开(公告)日：2013-05-23

申请号：US13740354

申请日：2013-01-14

申请人： Hiroyuki NAKAMURA ,  Akira MUTO ,  Nobuya KOIKE ,  Atsushi NISHIKIZAWA ,  Yukihiro SATO ,  Katsuhiko FUNATSU

发明人： Hiroyuki NAKAMURA ,  Akira MUTO ,  Nobuya KOIKE ,  Atsushi NISHIKIZAWA ,  Yukihiro SATO ,  Katsuhiko FUNATSU

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/495 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

摘要翻译： 为了防止在树脂密封型半导体封装中产生用于安装半导体芯片的芯片接合材料中的裂纹。 半导体芯片通过芯片接合材料安装在芯片焊盘的上表面上，然后用绝缘树脂密封。 要与绝缘树脂接触的芯片焊盘的顶表面被粗糙化，而芯片焊盘的底表面和外部引线部分没有被表面粗糙化。

公开(公告)号：US20100258922A1

公开(公告)日：2010-10-14

申请号：US12718200

申请日：2010-03-05

申请人： Hiroyuki NAKAMURA ,  Akira MUTO ,  Nobuya KOIKE ,  Atsushi NISHIKIZAWA ,  Yukihiro SATO ,  Katsuhiko FUNATSU

发明人： Hiroyuki NAKAMURA ,  Akira MUTO ,  Nobuya KOIKE ,  Atsushi NISHIKIZAWA ,  Yukihiro SATO ,  Katsuhiko FUNATSU

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L23/495 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

摘要翻译： 为了防止在树脂密封型半导体封装中产生用于安装半导体芯片的芯片接合材料中的裂纹。 半导体芯片通过芯片接合材料安装在芯片焊盘的上表面上，然后用绝缘树脂密封。 要与绝缘树脂接触的芯片焊盘的顶表面被粗糙化，而芯片焊盘的底表面和外部引线部分没有被表面粗糙化。

公开(公告)号：US20090317948A1

公开(公告)日：2009-12-24

申请号：US12432075

申请日：2009-04-29

申请人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

发明人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

IPC分类号： H01L21/50 ,  H01L21/60

CPC分类号： H01L21/4835 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3426 ,  H05K2201/10795 ,  H05K2201/10909 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and the tie bar is removed by a laser and thereafter a surface treatment such as solder plating is performed.

摘要翻译： 提供一种使用具有用于捆扎多个引线的外端部的连接杆的多器件引线框架来制造QFN型半导体集成电路器件的方法，其中填充在模腔的外周和连接杆之间的密封树脂是 通过激光去除，然后进行诸如焊料镀覆的表面处理。

公开(公告)号：US20110316137A1

公开(公告)日：2011-12-29

申请号：US13225788

申请日：2011-09-06

申请人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

发明人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

IPC分类号： H01L23/495

CPC分类号： H01L21/4835 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3426 ,  H05K2201/10795 ,  H05K2201/10909 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.

摘要翻译： 半导体器件包括半导体芯片，芯片安装部分，悬挂引线和多个引线。 多个引线中的每一个具有第一部分和第二部分，并且悬架引线具有第一部分和第二部分。 多个引线中的每一个的第一部分和悬挂引线分别从密封体的多个侧表面伸出。 多个引线的侧面部分和悬挂引线分别从密封体的多个侧面露出。 在俯视图中，悬架引线的第一部分的正面的面积大于多根引线中的每一个的第一部分的正面的面积。

公开(公告)号：US20080054422A1

公开(公告)日：2008-03-06

申请号：US11841955

申请日：2007-08-20

申请人： Nobuya KOIKE ,  Atsushi FUJIKI ,  Norio KIDO ,  Yukihiro SATO ,  Hiroyuki NAKAMURA

发明人： Nobuya KOIKE ,  Atsushi FUJIKI ,  Norio KIDO ,  Yukihiro SATO ,  Hiroyuki NAKAMURA

IPC分类号： H01L23/495

CPC分类号： H01L21/565 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device.A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

摘要翻译： 通过改变半导体器件的结构，安装时的安装布线的布局变得有效。 第一芯片安装在第一芯片焊盘上，第二芯片也安装在第二芯片焊盘上。 第一管芯焊盘和第二管芯焊盘与密封体40的第一侧面和第二侧平行地进行分割结构。 结果，用于从第一芯片输出的引脚和用于控制驱动电路的引脚可使其能够从相反方向突出，并且可以将安装时的布线布局设置为最小路线 。

公开(公告)号：US20120261825A1

公开(公告)日：2012-10-18

申请号：US13533391

申请日：2012-06-26

申请人： Nobuya KOIKE ,  Atsushi Fujiki ,  Norio Kido ,  Yukihiro Sato ,  Hiroyuki Nakamura

发明人： Nobuya KOIKE ,  Atsushi Fujiki ,  Norio Kido ,  Yukihiro Sato ,  Hiroyuki Nakamura

IPC分类号： H01L23/48

CPC分类号： H01L21/565 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device.A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

摘要翻译： 通过改变半导体器件的结构，安装时的安装布线的布局变得有效。 第一芯片安装在第一芯片焊盘上，第二芯片也安装在第二芯片焊盘上。 第一管芯焊盘和第二管芯焊盘与密封体40的第一侧面和第二侧平行地进行分割结构。结果，用于从第一芯片输出的引脚和用于控制驱动电路的引脚 可以使其能够从反方向投影，并可以将安装时的布线布局设置为最小路线。

公开(公告)号：US20110215400A1

公开(公告)日：2011-09-08

申请号：US13040234

申请日：2011-03-03

申请人： Hiroyuki NAKAMURA ,  Atsushi FUJIKI ,  Tatsuhiro SEKI ,  Nobuya KOIKE ,  Yukihiro SATO ,  Kisho ASHIDA

发明人： Hiroyuki NAKAMURA ,  Atsushi FUJIKI ,  Tatsuhiro SEKI ,  Nobuya KOIKE ,  Yukihiro SATO ,  Kisho ASHIDA

IPC分类号： H01L27/07 ,  H01L29/66

CPC分类号： H01L27/07 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/66 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.

摘要翻译： 提高半导体器件的性能和可靠性。 对于半导体芯片CP1，用于开关的功率MOSFET Q1和Q2，用于检测功率MOSFET Q1的发热的二极管DD1，用于检测功率MOSFET Q2的发热的二极管DD2和多个焊盘电极PD 。 功率MOSFET Q1和二极管DD1布置在侧面SD1侧的第一MOSFET区域RG1中，功率MOSFET Q2和二极管DD2布置在侧面SD2侧的第二MOSFET区RG2中。 二极管DD1沿着侧面SD1配置，二极管DD2沿着侧面SD2配置，除了用于源极的焊盘电极PDS1和PDS2以外的所有焊盘电极PD沿着二极管DD1和DD2之间的侧面SD3排列。

公开(公告)号：US20110143500A1

公开(公告)日：2011-06-16

申请号：US13035273

申请日：2011-02-25

申请人： Nobuya KOIKE ,  Tsukasa MATSUSHITA ,  Hiroshi SATO ,  Keiichi OKAWA ,  Atsushi NISHIKIZAWA

发明人： Nobuya KOIKE ,  Tsukasa MATSUSHITA ,  Hiroshi SATO ,  Keiichi OKAWA ,  Atsushi NISHIKIZAWA

IPC分类号： H01L21/60

CPC分类号： H01L23/49524 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/91 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/207

摘要： There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.

摘要翻译： 需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。 另外需要提供能够减少半导体器件的芯片尺寸的技术。 半导体芯片包括形成功率晶体管的功率晶体管形成区域，形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。 在功率晶体管形成区域中形成焊盘。 焊盘和引线通过横截面大于导线的夹子连接。 另一方面，焊盘通过导线29连接。

公开(公告)号：US20100308421A1

公开(公告)日：2010-12-09

申请号：US12767071

申请日：2010-04-26

申请人： Akira MUTO ,  Yuichi MACHIDA ,  Nobuya KOIKE ,  Atsushi FUJIKI ,  Masaki TAMURA

发明人： Akira MUTO ,  Yuichi MACHIDA ,  Nobuya KOIKE ,  Atsushi FUJIKI ,  Masaki TAMURA

IPC分类号： H01L27/088 ,  H01L23/52 ,  H01L23/28

CPC分类号： H01L25/074 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73253 ,  H01L2924/13091

摘要： The size of a semiconductor device is reduced. A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin portion. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with the area positioned directly above a gate pad electrode of the lower semiconductor chip. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other.

摘要翻译： 半导体器件的尺寸减小。 一种半导体芯片，其中功率MOSFET被放置在其上形成另一功率MOSFET的半导体芯片之上，并且它们被密封树脂​​部分密封。 半导体芯片被布置成使得上半导体芯片不与位于下半导体芯片的栅极焊盘电极正下方的区域重叠。 半导体芯片的尺寸相同，并且下半导体芯片和上半导体芯片的各个源极焊盘电极和栅极焊盘电极的形状和布置相同。 下半导体芯片和上半导体芯片被布置成它们各自的中心彼此偏离。

公开(公告)号：US20090057915A1

公开(公告)日：2009-03-05

申请号：US12197938

申请日：2008-08-25

申请人： Nobuya KOIKE ,  Shinya Nagata

发明人： Nobuya KOIKE ,  Shinya Nagata

IPC分类号： H01L23/48

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The operation stability of a SiP (semiconductor device) using a stacked packaging method for stacking a microcomputer IC chip over a driver IC chip is improved. In the SiP using the stacked packaging method for stacking the microcomputer IC chip over the driver IC chip, circuits sensitive to heat or noise, such as an analog to digital conversion circuit, a digital to analog conversion circuit, a sense amplifier circuit of a memory (RAM or ROM), and a power supply circuit of a microcomputer IC chip are prevented from two-dimensionally overlapping with a driver circuit of the lower-side driver IC chip. Since this can reduce, during the operation, the effect of heat or noise, which the circuits sensitive to heat or noise of the microcomputer IC chip receive from the driver circuit of the lower-side driver IC chip, the operation stability of the SiP (semiconductor device) using the stacked packaging method can be improved.

摘要翻译： 使用堆叠封装方法的SiP（半导体器件）在驱动器IC芯片上堆叠微计算机IC芯片的操作稳定性得到改善。 在使用堆叠封装方法的SiP中，将微计算机IC芯片堆叠在驱动器IC芯片上，对热或噪声敏感的电路如模数转换电路，数模转换电路，存储器的读出放大器电路 （RAM或ROM），并且防止微型计算机IC芯片的电源电路与下侧驱动IC芯片的驱动电路二维重叠。 由于这可以在操作期间减少由微机IC芯片的热或噪声敏感的电路从下侧驱动器IC芯片的驱动电路接收的热或噪声的影响，SiP的操作稳定性 半导体器件）可以提高。