公开(公告)号：US20090184420A1

公开(公告)日：2009-07-23

申请号：US12213466

申请日：2008-06-19

申请人： Jin-Won Choi ,  Chang-Sup Ryu ,  Seung-Hyun Cho ,  Seung-Wan Kim

发明人： Jin-Won Choi ,  Chang-Sup Ryu ,  Seung-Hyun Cho ,  Seung-Wan Kim

IPC分类号： H01L23/488 ,  H01L21/44 ,  H05K3/00 ,  H05K1/00

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0568 ,  H05K2203/0571 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

摘要： A post bump and a method of forming the post bump are disclosed. The method of forming the post bump can include: forming a resist layer, in which an aperture is formed in correspondence to a position of an electrode pad, over a substrate, on which the electrode pad is formed; forming a metal post by filling a part of the aperture with a metallic material; filling a remaining part of the aperture with solder; reflowing the solder by applying heat; and removing the resist layer. This method can be utilized to prevent deviations in the plated solder and prevent the unnecessary flowing of the solder over the sides of the metal post during reflowing, so that the amount of solder used can be minimized.

摘要翻译： 公开了一种后凸块和形成凸块的方法。 形成后凸块的方法可以包括：在其上形成有电极焊盘的基板上形成抗蚀剂层，其中形成有孔对应于电极焊盘的位置; 通过用金属材料填充孔的一部分来形成金属柱; 用焊料填充孔的剩余部分; 通过加热回流焊料; 并除去抗蚀剂层。 该方法可以用于防止电镀焊料中的偏差，并且防止在回流期间焊料在金属柱的侧面上不必要的流动，使得可以使所使用的焊料的量最小化。

公开(公告)号：US07983055B2

公开(公告)日：2011-07-19

申请号：US12010436

申请日：2008-01-24

申请人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

发明人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC分类号： H05K1/18 ,  H01L27/108

CPC分类号： H05K1/162 ,  H05K1/0218 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09972

摘要： A printed circuit board having an embedded cavity capacitor is disclosed. According to an embodiment of the present invention, the printed circuit board having the embedded cavity capacitor, the printed circuit board can include two conductive layers to be used as a power layer and a ground layer, respectively; and a first dielectric layer, placed between the two conductive layers, wherein at least one cavity capacitor is arranged in a noise-transferable path between a noise source and a noise prevented destination which are placed on the printed circuit board, the cavity capacitor being formed to allow a second dielectric layer to have a lower stepped region than the first dielectric layer, the second dielectric layer using the two conductive layers as a first electrode and a second electrode, respectively, and placed between the first electrode and the second electrode.

摘要翻译： 公开了一种具有嵌入式腔体电容器的印刷电路板。 根据本发明的实施例，具有嵌入式空腔电容器的印刷电路板，印刷电路板可以分别包括用作功率层和接地层的两个导电层; 以及放置在所述两个导电层之间的第一电介质层，其中至少一个空腔电容器被布置在放置在所述印刷电路板上的噪声源和被噪声阻止的目的地之间的可噪声转移路径中，形成所述空腔电容器 以允许第二电介质层具有比第一电介质层更低的台阶区域，第二电介质层分别使用两个导电层作为第一电极和第二电极，并且放置在第一电极和第二电极之间。

公开(公告)号：US20100212951A1

公开(公告)日：2010-08-26

申请号：US12654766

申请日：2009-12-31

申请人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

发明人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC分类号： H05K9/00

CPC分类号： H05K9/0071 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0236 ,  H05K9/002 ,  H05K9/0064 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An EMI noise reduction board using an electromagnetic bandgap structure is disclosed. In the EMI noise reduction board according to an embodiment of the present invention, an electromagnetic bandgap structure having band stop frequency properties can be inserted into an inner portion of the board so as to shield an EMI noise, in which the portion corresponds to an edge of the board and in which the EMI noise is conducted from the inside to the edge of the board and radiates to the outside of the board.

摘要翻译： 公开了一种使用电磁带隙结构的EMI降噪板。 在根据本发明实施例的EMI噪声抑制板中，具有带阻频率特性的电磁带隙结构可以插入到板的内部，以屏蔽EMI噪声，其中该部分对应于边缘 并且其EMI噪声从板的内部传导到边缘并辐射到板的外部。

公开(公告)号：US20090294739A1

公开(公告)日：2009-12-03

申请号：US12263685

申请日：2008-11-03

申请人： Eung-Suek Lee ,  Je-Gwang Yoo ,  Chang-Sup Ryu ,  Jun-Oh Hwang ,  Tae-Eun Chang ,  Jee-Soo Mok

发明人： Eung-Suek Lee ,  Je-Gwang Yoo ,  Chang-Sup Ryu ,  Jun-Oh Hwang ,  Tae-Eun Chang ,  Jee-Soo Mok

IPC分类号： H01B1/02

CPC分类号： H01B1/24 ,  B82Y10/00 ,  H05K1/095 ,  H05K3/4069 ,  H05K2201/026 ,  H05K2201/0272 ,  H05K2201/0323 ,  H05K2203/0425

摘要： The invention provides a conductive paste including a carbon nanotube and a printed circuit board using the same. The invention provides the conductive paste which exhibits an excellent electrical conductivity and allows the implementation of the X-Y interconnection and simultaneously the Z-interconnection without loosing the carbon nanotube's own original characteristics.

摘要翻译： 本发明提供一种包括碳纳米管的导电浆料和使用其的印刷电路板。 本发明提供了导电性优异的导电性糊剂，其导电性优异，可以实现X-Y互连，同时实现Z-互连，而不会使碳纳米管本身的原有特性丧失。

公开(公告)号：US07605459B2

公开(公告)日：2009-10-20

申请号：US11706223

申请日：2007-02-15

申请人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Dong-Jin Park

发明人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Dong-Jin Park

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L23/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/48237 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599

摘要： An aspect of the present invention features a manufacturing method of a package on package with a cavity. The method can comprise (a) forming a first upper substrate cavity in one side of an upper substrate; (b) mounting an upper semiconductor chip on the other side of the upper substrate; (c) forming a lower substrate cavity in one side of a lower substrate; (d) mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and (e) stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.

摘要翻译： 本发明的一个方面的特征在于具有空腔的封装的封装的制造方法。 该方法可以包括（a）在上基板的一侧中形成第一上基板空腔; （b）将上半导体芯片安装在上基板的另一侧上; （c）在下基板的一侧中形成下基板空腔; （d）将下半导体芯片安装在形成在下基板中的下基板空腔中; 和（e）将上基板堆叠在下基板上方，使得第一上基板空腔容纳下半导体芯片的一部分。 包装上的封装及其制造方法可以通过在上基板和下基板中形成空腔来容纳安装在下基板中的半导体芯片来减小封装的整体厚度。

公开(公告)号：US20090130390A1

公开(公告)日：2009-05-21

申请号：US12149952

申请日：2008-05-09

申请人： Joon-Sung Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu ,  Han-Seo Cho ,  Sang-Hoon Kim

发明人： Joon-Sung Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu ,  Han-Seo Cho ,  Sang-Hoon Kim

IPC分类号： B32B3/00 ,  B29D11/00

CPC分类号： B29D11/00663 ,  B29D11/00807 ,  G02B6/136 ,  H05K1/0274 ,  Y10T428/24612

摘要： An optical wiring board and a method of manufacturing the optical wiring board are disclosed. The method of manufacturing an optical wiring board may include forming a lower cladding over an insulating layer; forming a side cladding, which has an indentation corresponding with the core, over the lower cladding; filling a core material in the indentation; and forming an upper cladding such that the core material is covered. Embodiments of the invention can be utilized to readily control the thickness of the core.

摘要翻译： 公开了一种光布线板及其制造方法。 制造光布线板的方法可以包括在绝缘层上形成下包层; 在所述下包层上形成具有与所述芯对应的凹陷的侧包层; 填充压痕中的芯材; 并且形成上覆层，使得芯材被覆盖。 本发明的实施例可用于容易地控制芯的厚度。

公开(公告)号：US20070187810A1

公开(公告)日：2007-08-16

申请号：US11706223

申请日：2007-02-15

申请人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Dong-Jin Park

发明人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Dong-Jin Park

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/48237 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599

摘要： An aspect of the present invention features a manufacturing method of a package on package with a cavity. The method can comprise (a) forming a first upper substrate cavity in one side of an upper substrate; (b) mounting an upper semiconductor chip on the other side of the upper substrate; (c) forming a lower substrate cavity in one side of a lower substrate; (d) mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and (e) stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.

摘要翻译： 本发明的一个方面的特征在于具有空腔的封装的封装的制造方法。 该方法可以包括（a）在上基板的一侧中形成第一上基板空腔; （b）将上半导体芯片安装在上基板的另一侧上; （c）在下基板的一侧中形成下基板空腔; （d）将下半导体芯片安装在形成在下基板中的下基板空腔中; 和（e）将上基板堆叠在下基板上方，使得第一上基板空腔容纳下半导体芯片的一部分。 封装上的封装及其制造方法可以通过在上基板和下基板中形成空腔来容纳安装在下基板中的半导体芯片来减小封装的整体厚度。

公开(公告)号：US20070059917A1

公开(公告)日：2007-03-15

申请号：US11520729

申请日：2006-09-14

申请人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Ki-Hwan Kim ,  Sung-Yong Kim

发明人： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Ki-Hwan Kim ,  Sung-Yong Kim

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H05K3/4664 ,  H05K3/0023 ,  H05K3/1216 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/465 ,  H05K2201/09536 ,  H05K2203/0143 ,  H05K2203/0568

摘要： A manufacturing method for a printed circuit board having a fine pattern is disclosed, comprising: providing a carrier plate; coating the carrier plate with a photosensitive material; forming a first circuit pattern on the photosensitive material; forming a first circuit layer by drying a conductive paste printed into a space between the photosensitive materials where the first circuit pattern is formed; depositing an insulation layer on the first circuit layer; processing via holes penetrating the insulation layer; coating the insulation layer with the photosensitive material and then forming a second circuit pattern in the photosensitive material; forming a second circuit layer and filling the via holes by drying the conductive paste printed into a space between the photosensitive materials, where the second circuit pattern is formed, and the via holes; and removing the carrier plate.

摘要翻译： 公开了一种具有精细图案的印刷电路板的制造方法，包括：提供载板; 用感光材料涂覆载体板; 在感光材料上形成第一电路图案; 通过干燥印刷在形成有第一电路图案的感光材料之间的空间中的导电浆料形成第一电路层; 在第一电路层上沉积绝缘层; 通过贯穿绝缘层的孔加工; 用感光材料涂覆绝缘层，然后在感光材料中形成第二电路图案; 形成第二电路层，并通过干燥印刷在其中形成第二电路图案的感光材料之间的空间中的导电浆料和通孔来填充通孔; 并移除载体板。

公开(公告)号：US08966746B2

公开(公告)日：2015-03-03

申请号：US13064847

申请日：2011-04-20

申请人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

发明人： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC分类号： H05K3/30 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC分类号： H05K1/162 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.

摘要翻译： 一种嵌入在印刷电路板中的空腔电容器的方法，包括分别用作功率层和接地层的两个导电层和放置在两个导电层之间的第一介电层，所述方法包括： 上导电层和除了两个导电层的下导电层之外的第一电介质层，以允许在两个导电层之间形成腔，下导电层假定用作空腔电容器的任一电极; 在所述空腔上堆叠电介质材料以允许在所述空腔中形成具有比所述第一电介质层更低的台阶部分的第二电介质层; 并且在第二电介质层的上部和空腔的侧部上堆叠导电材料，以允许上部导电层用作空腔电容器的另一个电极。

公开(公告)号：US08499444B2

公开(公告)日：2013-08-06

申请号：US12216152

申请日：2008-06-30

申请人： Jin-Yong An ,  Chang-Sup Ryu ,  Jong-Kuk Hong

发明人： Jin-Yong An ,  Chang-Sup Ryu ,  Jong-Kuk Hong

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K1/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0097 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T428/24851 ,  Y10T428/24917 ,  H01L2924/00

摘要： A package substrate and a method of manufacturing the package substrate are disclosed. The method of manufacturing the package substrate may include stacking a second metal layer in which at least one hole is formed over a first metal layer, stacking a barrier layer over the first metal layer exposed in the hole and over the second metal layer, forming at least one bump by filling the hole with a conductive metal, stacking an insulation layer over the bump and forming a circuit pattern over the insulation layer, and removing the first metal layer, the second metal layer, and the barrier layer.

摘要翻译： 公开了封装基板和制造封装基板的方法。 制造封装衬底的方法可以包括堆叠第二金属层，其中在第一金属层上形成至少一个孔，在第一金属层上方在第二金属层上方堆叠阻挡层，形成在第二金属层上 通过用导电金属填充所述孔至少一个凸块，在所述凸块上方堆叠绝缘层并在所述绝缘层上形成电路图案，以及去除所述第一金属层，所述第二金属层和所述阻挡层。