公开(公告)号：US06732908B2

公开(公告)日：2004-05-11

申请号：US10052591

申请日：2002-01-18

申请人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： Bruce Kenneth Furman ,  Maheswaran Surendra ,  Sherif A. Goma ,  Simon M. Karecki ,  John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： B23K3102

CPC分类号： H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.

摘要翻译： 一个微型接头互连结构，包括具有精确可控高度的密集阵列的金属螺柱，并具有接合冶金。 该阵列在要连接到载体的装置芯片上或与其他装置一起在载体上产生，其中一些装置芯片可被选择为具有相似的互连结构，以便将组装的载体形成为一体， 完整的计算，通信或网络系统。

公开(公告)号：US06661098B2

公开(公告)日：2003-12-09

申请号：US10052620

申请日：2002-01-18

申请人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

摘要翻译： 教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。 载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。

公开(公告)号：US06819000B2

公开(公告)日：2004-11-16

申请号：US10692065

申请日：2003-10-23

申请人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

摘要翻译： 教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。 载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片采用微连接焊盘阵列，其包括粘附层，阻挡层和易熔焊料层，焊盘位于相对于阻挡插座的匹配位置; 器件芯片通过微接点阵列连接到载体，导致能够具有非常高的输入/输出密度和芯片间布线密度的互连。

公开(公告)号：US06747472B2

公开(公告)日：2004-06-08

申请号：US10052619

申请日：2002-01-18

申请人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

发明人： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

IPC分类号： G01R3126

CPC分类号： H01L24/11 ,  G01R1/0416 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/325 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

摘要翻译： 一种用于通过将装置芯片临时附接到具有多个具有微树突状特征的容器的载体来测试装置芯片集合的系统; 所述插座与所述器件芯片上的匹配的接触焊盘组匹配并且与所述插座接触; 所述载体另外具有通过互连布线连接到插座的测试垫。 该系统允许将芯片连接在一起，并通过探测载体上的测试垫来整体测试集合。 芯片集合的老化也可以在临时载体上执行，这是可重复使用的。

公开(公告)号：US07880305B2

公开(公告)日：2011-02-01

申请号：US10290049

申请日：2002-11-07

申请人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

发明人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

公开(公告)号：US20090302454A1

公开(公告)日：2009-12-10

申请号：US12462980

申请日：2009-08-11

申请人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

发明人： Yu- Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

公开(公告)号：US20060267208A1

公开(公告)日：2006-11-30

申请号：US11405283

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

摘要翻译： 描述了形成闭合气隙互连结构的方法。 在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板 孔阵列 然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。 通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。 描述该方法的几个实施例和所得到的结构。

公开(公告)号：US20060258147A1

公开(公告)日：2006-11-16

申请号：US11405287

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

公开(公告)号：US20050062165A1

公开(公告)日：2005-03-24

申请号：US10666564

申请日：2003-09-19

申请人： Katherine Saenger ,  Maheswaran Surendra ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Matthew Colburn ,  Timothy Dalton ,  Elbert Huang

发明人： Katherine Saenger ,  Maheswaran Surendra ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Matthew Colburn ,  Timothy Dalton ,  Elbert Huang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

摘要翻译： 描述了形成闭合气隙互连结构的方法。 与存在于所述互连结构的其余部分的一个或多个牺牲介电质制成的互连线下永久支撑电介质的区域和周围的互连通孔的起始结构，覆盖有其使用模版具有规则穿孔的电介质阻挡 孔阵列 然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。 通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。 描述该方法的几个实施例和所得到的结构。

公开(公告)号：US20080280416A1

公开(公告)日：2008-11-13

申请号：US12180827

申请日：2008-07-28

申请人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

发明人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

IPC分类号： H01L21/30 ,  H01L21/822

CPC分类号： H01L21/76259 ,  Y10T428/249961

摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.

摘要翻译： 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调节孔隙度的多孔区域的载体衬底和在其中限定分离平面的注入物质的组合。 另一方面，提供了一种形成层转移结构的方法。 另一方面，提供一种形成三维一体化结构的方法。