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    Interconnect arrangement and associated production methods
    2.
    发明授权
    Interconnect arrangement and associated production methods 有权
    互连安排和相关生产方式

    公开(公告)号：US08877631B2

    公开(公告)日：2014-11-04

    申请号：US13110022

    申请日：2011-05-18

    申请人： Manfred Engelhardt ,  Werner Pamler ,  Guenther Schindler

    发明人： Manfred Engelhardt ,  Werner Pamler ,  Guenther Schindler

    IPC分类号： H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L27/108

    CPC分类号： H01L21/7681 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.

    摘要翻译： 描述了互连装置和制造方法。 互连装置包括导电安装基板，形成在安装基板上的电介质层和形成在电介质层上的导电布线。 互连下方的电介质层的至少一部分包含空腔。 为了制造互连布置，在安装基板上形成牺牲层，并且在牺牲层上形成互连层。 互连层和牺牲层被构造成在结构化牺牲层上产生结构化互连。 在安装基板和结构化互连的表面以及牺牲层上形成多孔电介质层。 然后去除牺牲层以在互连下形成空腔。

    MIM capacitor and associated production method
    4.
    发明授权
    MIM capacitor and associated production method 有权
    MIM电容器及相关生产方法

    公开(公告)号：US08709906B2

    公开(公告)日：2014-04-29

    申请号：US13342120

    申请日：2012-01-02

    申请人： Manfred Engelhardt ,  Andreas Stich ,  Guenther Schindler ,  Michael Schrenk

    发明人： Manfred Engelhardt ,  Andreas Stich ,  Guenther Schindler ,  Michael Schrenk

    IPC分类号： H01L21/20

    CPC分类号： H01G4/33 ,  H01G4/228 ,  H01G4/40 ,  H01L28/75

    摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.

    摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容器电介质和第二电容器电极。

    Methods of Forming Semiconductor Devices
    5.
    发明申请
    Methods of Forming Semiconductor Devices 有权
    形成半导体器件的方法

    公开(公告)号：US20130189830A1

    公开(公告)日：2013-07-25

    申请号：US13355003

    申请日：2012-01-20

    申请人： Joachim Hirschler ,  Michael Roesner ,  Manfred Engelhardt

    发明人： Joachim Hirschler ,  Michael Roesner ,  Manfred Engelhardt

    IPC分类号： H01L21/78

    CPC分类号： H01L21/568 ,  H01L21/31138 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.

    摘要翻译： 根据本发明的实施例，制造半导体器件的方法包括从具有器件区域的衬底的顶表面形成沟槽。 器件区域与顶表面相邻，而不是相对的底表面。 沟槽围绕设备区域的侧壁。 沟槽填充有粘合剂。 在衬底的顶表面上形成粘合剂层。 载体附着有粘合剂层。 衬底从底表面变薄以暴露粘合剂的至少一部分和器件区域的后表面。 去除粘合剂层并蚀刻粘合剂以露出装置区域的侧壁。