公开(公告)号：US6025650A

公开(公告)日：2000-02-15

申请号：US961243

申请日：1997-10-30

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Junichi Kasai

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Junichi Kasai

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48 ,  H01L29/41

CPC分类号： H01L21/6835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/49 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件包括具有多个焊盘的半导体芯片，密封所述半导体芯片的树脂部分和设置有电连接到设置在所述半导体芯片中的所述焊盘的规定数量的极端子的端子部分，所述极端子露出 从所述树脂部分。 根据本发明，生产成本降低，并且可以提高可靠性和电气特性。

公开(公告)号：US5656550A

公开(公告)日：1997-08-12

申请号：US611007

申请日：1996-03-05

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L21/60

CPC分类号： H01L24/49 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/49121

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件具有半导体芯片，具有引线部分的引线部分和与引线部分整体连接的外部连接端子，引线部分电连接到半导体芯片，引线部分从半导体芯片向外延伸，外部连接 从所述引线部分向下延伸的端子，密封所述半导体芯片和所述引线部分的密封树脂，所述半导体芯片的底面和所述引线部分的底面从所述密封树脂露出;以及绝缘构件， 和半导体芯片的底面。 此外，半导体器件具有预定数量的电极焊盘的半导体芯片，与电极焊盘电连接的预定数量的引线，每个引线具有通过弯曲引线形成的突出端子部分和密封 半导体芯片和引线，其中端子部分从树脂部分的一个面露出。

公开(公告)号：US06255740B1

公开(公告)日：2001-07-03

申请号：US08847222

申请日：1997-05-01

申请人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

发明人： Kazuto Tsuji ,  Yoshiyuki Yoneda ,  Hideharu Sakoda ,  Ryuji Nomoto ,  Eiji Watanabe ,  Seiichi Orimo ,  Masanori Onodera ,  Masaki Waki

IPC分类号： H01L2329

CPC分类号： H01L24/49 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

摘要： This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.

摘要翻译： 本发明涉及一种半导体器件，其中多个外部端子以平坦表面的格子状排列。 半导体器件具有半导体芯片，具有引线部分的引线部分和与引线部分整体连接的外部连接端子，引线部分电连接到半导体芯片，引线部分从半导体芯片向外延伸，外部连接 从所述引线部分向下延伸的端子，密封所述半导体芯片和所述引线部分的密封树脂，所述半导体芯片的底面和所述引线部分的底面从所述密封树脂露出;以及绝缘构件， 和半导体芯片的底面。 此外，半导体器件具有预定数量的电极焊盘的半导体芯片，与电极焊盘电连接的预定数量的引线，每个引线具有通过弯曲引线形成的突出端子部分和密封 半导体芯片和引线，其中端子部分从树脂部分的一个面露出。

公开(公告)号：US06218281B1

公开(公告)日：2001-04-17

申请号：US09192443

申请日：1998-11-16

申请人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

发明人： Eiji Watanabe ,  Hirohisa Matsuki ,  Kenichi Kado ,  Kenichi Nagashige ,  Masanori Onodera ,  Kunio Kodama ,  Hiroyuki Yoda ,  Joji Fujimori ,  Minoru Nakada ,  Yutaka Makino

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.

摘要翻译： 制备半导体衬底，其具有主表面，由导电材料制成的裸露焊盘形成在主表面的局部区域中，并且主表面的另一区域被第一绝缘膜覆盖。 在第一绝缘膜和垫上形成基底导电膜。 在基底导电膜上形成厚度为50μm以上的光刻胶膜。 在与该焊盘相对应的区域中形成通过光致抗蚀剂膜的开口以暴露基底导电膜的部分表面区域。 导电凸块电极沉积在暴露在开口底部的基底导电膜上。 除去光致抗蚀剂膜。 该方法适用于在凸块电极之间形成细间距。

公开(公告)号：US07754534B2

公开(公告)日：2010-07-13

申请号：US12081723

申请日：2008-04-21

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L21/00

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

摘要翻译： 提供一种使用布线基板制造半导体器件的方法，其可以有助于布线基板的处理。 该方法包括以下步骤：在硅基板上形成可剥离树脂层，在可剥离树脂层上形成布线基板，在布线基板上安装半导体芯片，通过密封树脂密封多个半导体芯片形成半导体器件， 半导体器件通过从密封树脂侧切割半导体器件但离开硅衬底，从硅衬底和可剥离树脂层之间的硅衬底剥离每个单独的半导体器件，并且通过形成开口 通过可剥离树脂层或通过除去可剥离树脂层。

公开(公告)号：US06905951B2

公开(公告)日：2005-06-14

申请号：US10862403

申请日：2004-06-08

申请人： Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

发明人： Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/14 ,  H01L23/31 ,  H01L23/32 ,  H01L23/498 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/6835 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

摘要翻译： 半导体器件基板具有细小的间距的端子，并且能够在不使用特殊工艺的情况下以低成本容易地制造。 安装端子具有金字塔形状并且在硅衬底的前表面和后表面之间延伸。 安装端子的一端从硅衬底的背面突出。 在硅衬底的前表面上形成布线层。 布线层包括电连接到安装端子的导电层。

公开(公告)号：US06781224B2

公开(公告)日：2004-08-24

申请号：US10262074

申请日：2002-10-02

申请人： Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

发明人： Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

IPC分类号： H01L2302

CPC分类号： H01L21/6835 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

摘要翻译： 半导体器件基板具有细小的间距的端子，并且能够在不使用特殊工艺的情况下以低成本容易地制造。 安装端子具有金字塔形状并且在硅衬底的前表面和后表面之间延伸。 安装端子的一端从硅衬底的背面突出。 在硅衬底的前表面上形成布线层。 布线层包括电连接到安装端子的导电层。

公开(公告)号：US20080261336A1

公开(公告)日：2008-10-23

申请号：US12081723

申请日：2008-04-21

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L21/66 ,  H01L21/56

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

摘要翻译： 提供一种使用布线基板制造半导体器件的方法，其可以有助于布线基板的处理。 该方法包括以下步骤：在硅基板上形成可剥离树脂层，在可剥离树脂层上形成布线基板，在布线基板上安装半导体芯片，通过密封树脂密封多个半导体芯片形成半导体器件， 半导体器件通过从密封树脂侧切割半导体器件但离开硅衬底，从硅衬底和可剥离树脂层之间的硅衬底剥离每个单独的半导体器件，并且通过形成开口 通过可剥离树脂层或通过除去可剥离树脂层。

公开(公告)号：US06794273B2

公开(公告)日：2004-09-21

申请号：US10331560

申请日：2002-12-31

申请人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

发明人： Nobukatsu Saito ,  Masaharu Minamizawa ,  Yoshiyuki Yoneda ,  Nobutaka Shimizu ,  Kazuyuki Imamura ,  Atsushi Kikuchi ,  Tadahiro Okamoto ,  Eiji Watanabe

IPC分类号： H01L2178

CPC分类号： H01L21/6836 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75315 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

公开(公告)号：US08865938B2

公开(公告)日：2014-10-21

申请号：US13877595

申请日：2011-10-05

申请人： Naritoshi Yoshimura ,  Shinji Kiyono ,  Tetsuya Hamada ,  Eiji Watanabe ,  Saiko Sawada

发明人： Naritoshi Yoshimura ,  Shinji Kiyono ,  Tetsuya Hamada ,  Eiji Watanabe ,  Saiko Sawada

IPC分类号： C07C209/00 ,  C07C209/48 ,  C07C253/22

CPC分类号： C07C209/48 ,  C07C253/22 ,  C07C2601/14 ,  C07C255/46 ,  C07C211/18

摘要： A method for producing bis(aminomethyl)cyclohexanes includes a nuclear hydrogenation step of producing hydrogenated phthalic acids or phthalic acid derivatives by nuclear hydrogenation of phthalic acids or phthalic acid derivatives of at least one selected from the group consisting of phthalic acids, phthalic acid esters, and phthalic acid amides; a cyanation step of treating the hydrogenated phthalic acids or phthalic acid derivatives obtained in the nuclear hydrogenation step with ammonia, thereby producing dicyanocyclohexanes; and an aminomethylation step of treating the dicyanocyclohexanes obtained in the cyanation step with hydrogen, thereby producing bis(aminomethyl)cyclohexanes. In the cyanation step, metal oxide is used as a catalyst, and the obtained dicyanocyclohexanes have a metal content of 3000 ppm or less.

摘要翻译： 制备双（氨基甲基）环己烷的方法包括核氢化步骤，其通过邻苯二甲酸或邻苯二甲酸衍生物的核氢化制备氢化邻苯二甲酸或邻苯二甲酸衍生物，所述邻苯二甲酸或邻苯二甲酸衍生物选自邻苯二甲酸，邻苯二甲酸酯， 和邻苯二甲酸酰胺; 氰化步骤，用氨处理在核氢化步骤中得到的氢化邻苯二甲酸或邻苯二甲酸衍生物，从而产生二氰基环己烷; 和在氰化步骤中用氢处理二氰基环己烷的氨基甲基化步骤，从而产生双（氨基甲基）环己烷。 在氰化步骤中，使用金属氧化物作为催化剂，所得到的二氰基环己烷的金属含量为3000ppm以下。