公开(公告)号：US20020034620A1

公开(公告)日：2002-03-21

申请号：US09965768

申请日：2001-09-27

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Hiroaki Takezawa ,  Tsutomu Mitani ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Kazuo Eda

IPC: B32B003/00

CPC classification number: H05K3/321 ,  B32B7/02 ,  B32B7/12 ,  H05K2201/09909 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2203/0783 ,  H05K2203/121 ,  Y02P70/611 ,  Y10S428/901 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T428/24066 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24975 ,  Y10T428/269 ,  Y10T428/31678 ,  Y10T428/31681

Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.

Abstract translation: 在包括通过导电粘合剂彼此电连接的第一电极和第二电极的安装结构中，至少一个电极和导电粘合剂之间的粘合部分的周边被电绝缘层覆盖，由此附着 部分从外围加强。 电绝缘层可以通过将导电粘合剂的粘合剂树脂组分溶解在溶剂中而形成。 这增加了导电粘合剂中的导电填料的浓度，从而也增强了粘合部分的导电性。

公开(公告)号：US20030207073A1

公开(公告)日：2003-11-06

申请号：US10409400

申请日：2003-04-07

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Hiroaki Takezawa ,  Tsutomu Mitani ,  Minehiro Itagaki ,  Yoshihiro Bessho ,  Kazuo Eda

IPC: B32B005/12 ,  B32B009/00 ,  B05D005/10 ,  B05D001/36

CPC classification number: H05K3/321 ,  B32B7/02 ,  B32B7/12 ,  H05K2201/09909 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2203/0783 ,  H05K2203/121 ,  Y02P70/611 ,  Y10S428/901 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T428/24066 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24975 ,  Y10T428/269 ,  Y10T428/31678 ,  Y10T428/31681

Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.

公开(公告)号：US20020081830A1

公开(公告)日：2002-06-27

申请号：US10086210

申请日：2002-02-27

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Yoshihiro Bessho

IPC: H01L021/44

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L21/76888 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

Abstract: An electrode structure for a semiconductor device and a method for forming the electrode structure, and a mounted body including the semiconductor device are provided in which the semiconductor device can be easily connected to a circuit board with high reliability. An aluminum electrode is formed on an IC substrate. A passivation film is formed on the IC substrate so as to cover the peripheral portion of the aluminum electrode. A bump electrode is formed on the aluminum electrode by a wire bonding method. An aluminum oxide film is formed on the surface of the aluminum electrode that is exposed around the bump electrode. A conductive adhesive is applied as a bonding layer to the tip portion of the bump electrode of the semiconductor device by a transfer method or a printing method. The semiconductor device is aligned in the face-down state in such a manner that the bump electrode abuts on a terminal electrode of a circuit board, and is provided on a circuit board. In this state, the conductive adhesive is hardened. A gap between the IC substrate and the circuit board is filled with an insulating resin.

公开(公告)号：US20020072151A1

公开(公告)日：2002-06-13

申请号：US10062463

申请日：2002-02-05

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Kazuyoshi Amami ,  Tsukasa Shiraishi ,  Yoshihiro Bessho

IPC: H01L021/44 ,  H01L021/48

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/305 ,  H05K3/321 ,  H01L2924/00014

Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.

公开(公告)号：US20030066683A1

公开(公告)日：2003-04-10

申请号：US10280964

申请日：2002-10-25

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Takeshi Suzuki ,  Tatsuo Ogawa ,  Yoshihiro Bessho ,  Satoru Tomekawa ,  Yasuhiro Nakatani ,  Yoji Ueda ,  Susumu Matsuoka ,  Daizo Andoh ,  Fumio Echigo

IPC: H05K001/11

CPC classification number: H05K1/0373 ,  H05K1/036 ,  H05K3/20 ,  H05K3/202 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part. According to this configuration, a part of the metal foil is embedded in the insulator layer so as to be in contact with the core layer. Therefore, this makes it possible to provide a circuit board in which portions of the conductive material can be selectively compressed, and which hence is capable of ensuring stable connection between layers.

公开(公告)号：US20010033032A1

公开(公告)日：2001-10-25

申请号：US09842487

申请日：2001-04-25

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Masahiro Ono ,  Tsukasa Shiraishi ,  Yoshihiro Bessho ,  Kazuo Eda

IPC: H01L023/52

CPC classification number: H01L24/85 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/81191 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A manufacturing method for a semiconductor device using a wire bonding method using a metal wire. In the wire bonding method, an impact load applied when a metal ball formed at the tip of the metal wire by electric discharge is brought into contact with a terminal electrode of a semiconductor device is smaller than a static load applied after the metal ball is brought into contact with the terminal electrode. The method makes it possible to prevent an element or wiring from being damaged while securing the pressure necessary for bonding the metal ball to the terminal electrode even when the terminal electrode is placed on the element or the wiring.

公开(公告)号：US20040040740A1

公开(公告)日：2004-03-04

申请号：US10654343

申请日：2003-09-03

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Seiichi Nakatani ,  Yoshihiro Bessho ,  Yasuhiro Sugaya ,  Keiji Onishi

IPC: H05K001/03 ,  H05K001/09

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/187 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/10378 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49146 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: At least two electric elements (203) such as semiconductor chips or surface acoustic wave devices are mounted on wiring patterns (201), and the electric elements (203) are sealed with a thermosetting resin composition (204). An upper surface of the at least two electric elements (203) and an upper surface of the thermosetting resin composition (204) are abraded at the same time, thereby forming surfaces substantially flush with each other. Since they are abraded while being sealed with the thermosetting resin composition (204), it is possible to reduce the thickness without damaging the electric elements (203). Also, the electric elements (203) and the wiring patterns (201) can be prevented from being contaminated by an abrasive liquid. In this manner, it is possible to obtain an electric element built-in module whose thickness can be reduced while maintaining its mechanical strength.

Abstract translation: 至少两个电子元件（203）如半导体芯片或表面声波器件安装在布线图案（201）上，电气元件（203）用热固性树脂组合物（204）密封。 所述至少两个电气元件（203）的上表面和所述热固性树脂组合物（204）的上表面同时被磨损，从而形成彼此基本齐平的表面。 由于它们在用热固性树脂组合物（204）密封的同时被磨损，所以可以减小厚度而不损坏电气元件（203）。 此外，可以防止电气元件（203）和布线图案（201）被研磨液体污染。 以这种方式，可以获得能够在保持其机械强度的同时减小其厚度的电子元件内置模块。

公开(公告)号：US20020101304A1

公开(公告)日：2002-08-01

申请号：US09971102

申请日：2001-10-03

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Keiji Onishi ,  Akihiro Nanba ,  Hiroki Sato ,  Katsunori Moritoki ,  Yoshihiro Bessho ,  Kunihiro Fujii ,  Kouzou Murakami

IPC: H03H009/00

CPC classification number: H03H9/1085 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/15174 ,  H01L2924/181 ,  H03H9/02559 ,  H03H9/0542 ,  H03H9/0547 ,  H03H9/0557 ,  H03H9/059 ,  H03H9/1092 ,  Y10T29/42 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01079

Abstract: A surface acoustic wave device of the present invention includes a piezoelectric substrate, a plurality of comb electrodes for exciting a surface acoustic wave, disposed on a principal plane of the piezoelectric substrate, a plurality of bumps disposed on the principal plane, and an insulating sheet disposed so as to be opposed to the principal plane, wherein the bumps and the comb electrodes are connected electrically to each other, and the bumps penetrate through the insulating sheet.

Abstract translation: 本发明的声表面波装置包括：压电基板，设置在压电基板的主面上的多个用于激励表面声波的梳形电极，设置在主平面上的多个凸块和绝缘片 被设置为与主平面相对，其中凸块和梳电极彼此电连接，并且凸块穿过绝缘片。

公开(公告)号：US20020038725A1

公开(公告)日：2002-04-04

申请号：US09928869

申请日：2001-08-13

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Takeshi Suzuki ,  Tatsuo Ogawa ,  Yoshihiro Bessho ,  Satoru Tomekawa ,  Yasuhiro Nakatani ,  Yoji Ueda ,  Susumu Matsuoka ,  Daizo Andoh ,  Fumio Echigo

IPC: H05K001/11

CPC classification number: H05K1/0373 ,  H05K1/036 ,  H05K3/20 ,  H05K3/202 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part. According to this configuration, a part of the metal foil is embedded in the insulator layer so as to be in contact with the core layer. Therefore, this makes it possible to provide a circuit board in which portions of the conductive material can be selectively compressed, and which hence is capable of ensuring stable connection between layers.

Abstract translation: 电路板被构造成在布线层之间包括不少于两个布线层，用于电绝缘的绝缘体层和在绝缘体层的厚度方向上设置在绝缘体层中的内通孔导电构件， 用于布线层之间的电连接。 绝缘体层由包含有机树脂和热膨胀系数小于有机树脂的材料的复合材料制成，并且包括以所述顺序层压的表面部分，芯部分和表面部分， 表面部分具有高含量的有机树脂，芯部分的有机树脂含量低。 所述布线层具有与所述内通孔导电部件连接的台面部，所述接合部嵌入以与所述芯部大体接触，所述内通孔导电部件的厚度基本上 等于芯部的厚度。 根据该结构，将金属箔的一部分嵌入到绝缘体层中以与芯层接触。 因此，能够提供能够选择性地压缩导电材料的部分的电路基板，由此能够确保层之间的稳定的连接。