公开(公告)号：US06476502B2

公开(公告)日：2002-11-05

申请号：US09517050

申请日：2000-03-02

申请人： Satoshi Yamada ,  Michitaka Kimura ,  Masatoshi Yasunaga

发明人： Satoshi Yamada ,  Michitaka Kimura ,  Masatoshi Yasunaga

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： An insulating resin sheet made from a thermosetting resin is provided on an insulating substrate in such a manner as to cover bonding pads provided on the insulating substrate. A lower chip is set on the insulating substrate in such a manner that bonding bumps connected to inner connection terminals of the lower chip break the insulating resin sheet 24 to be in contact with the bonding pads. The insulating resin sheet is thermally cured and subsequently the bonding bumps are melted.

摘要翻译： 在绝缘基板上设置由热固性树脂制成的绝缘树脂片，以覆盖设置在绝缘基板上的接合焊盘。 将下部芯片设置在绝缘基板上，使得与下部芯片的内部连接端子连接的接合凸块将绝缘树脂片材24与接合焊盘接触。 绝缘树脂板被热固化，随后粘合凸块熔化。

公开(公告)号：US06462425B1

公开(公告)日：2002-10-08

申请号：US09429635

申请日：1999-10-29

申请人： Toshihiro Iwasaki ,  Masatoshi Yasunaga ,  Satoshi Yamada ,  Kozo Harada ,  Michitaka Kimura

发明人： Toshihiro Iwasaki ,  Masatoshi Yasunaga ,  Satoshi Yamada ,  Kozo Harada ,  Michitaka Kimura

IPC分类号： H01L2940

CPC分类号： H01L21/563 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device allowing a mounting of a semiconductor substrate with narrow electrode pad interval on an insulated circuit board while securing a favorable insulation characteristic and a manufacturing method thereof are obtained. The semiconductor device includes an electrode pad formed on a semiconductor substrate; a connecting underlying metal film connected to the electrode pad; a connecting conductor establishing electrical conduction between the connecting underlying metal film and a terminal electrode on an insulated circuit board; and non-conductive resin surrounding the connecting conductor and filling a gap between the substrate and the insulated circuit board. Here, the connecting underlying metal film is not covered by the connecting conductor at least in a peripheral region including an outer peripheral portion thereof

摘要翻译： 获得能够在确保良好的绝缘特性的同时将具有窄电极焊盘间隔的半导体衬底安装在绝缘电路板上的半导体器件及其制造方法。 半导体器件包括形成在半导体衬底上的电极焊盘; 连接到电极焊盘的连接底层金属膜; 连接导体，其在连接的底层金属膜和绝缘电路板上的端子电极之间建立导电; 以及围绕连接导体的非导电树脂，并填充衬底和绝缘电路板之间的间隙。 这里，至少在包括其外周部分的周边区域中，连接基底金属膜不被连接导体覆盖

公开(公告)号：US06768516B2

公开(公告)日：2004-07-27

申请号：US09732925

申请日：2000-12-11

申请人： Satoshi Yamada ,  Michitaka Kimura ,  Naoto Ueda ,  Masatoshi Yasunaga

发明人： Satoshi Yamada ,  Michitaka Kimura ,  Naoto Ueda ,  Masatoshi Yasunaga

IPC分类号： H04N5225

CPC分类号： H04N5/2257 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2924/00014

摘要： The invention is intended for rendering a CMOS camera compact and less costly. A semiconductor device constituting a CMOS camera system includes a lens unit which includes a wiring board having an image pick-up opening formed therein and a lens, and the lens is provided on one side of the wiring board and positioned opposite the image pick-up opening. An image pick-up semiconductor is provided on the other side of the wiring board, and is positioned opposite the image pick-up opening, and is connected to a connection section of the wiring board by means of flip-chip bonding. An image processing semiconductor is connected by means of flip-chip bonding to another connection section provided on the other side of the wiring board, and processes an image signal output from the image pick-up semiconductor.

摘要翻译： 本发明旨在使CMOS相机紧凑且成本更低。 构成CMOS照相机系统的半导体器件包括透镜单元，该透镜单元包括其中形成有摄像开口的布线板和透镜，并且透镜设置在布线板的一侧并与图像拾取器相对定位 开放 在接线板的另一侧设置摄像半导体，与摄像开口相对设置，并通过倒装芯片接合而与布线基板的连接部连接。 图像处理半导体通过倒装芯片接合连接到设置在布线板的另一侧的另一连接部分，并处理从摄像半导体输出的图像信号。

公开(公告)号：US06544814B1

公开(公告)日：2003-04-08

申请号：US09494361

申请日：2000-01-31

申请人： Masatoshi Yasunaga ,  Michitaka Kimura ,  Satoshi Yamada

发明人： Masatoshi Yasunaga ,  Michitaka Kimura ,  Satoshi Yamada

IPC分类号： H01L2144

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A plurality of semiconductor chips are mounted on an insulating substrate with bumps and through use of dielectric resin for mounting purposes. The semiconductor chips are sealed with transfer mold resin through a single operation while remaining on the insulating substrate. Then, the plurality of semiconductor chips are separated together with the insulating substrate and the mounting resin into individual semiconductor devices. The productivity and reliability of packaged semiconductor devices is improved.

摘要翻译： 多个半导体芯片安装在具有凸块的绝缘基板上，并且通过使用用于安装目的的电介质树脂。 半导体芯片通过一次操作用传输模塑树脂密封，同时保留在绝缘基板上。 然后，将多个半导体芯片与绝缘基板和安装树脂一起分离成单独的半导体器件。 提高了封装半导体器件的生产率和可靠性。

公开(公告)号：US06856028B1

公开(公告)日：2005-02-15

申请号：US09665415

申请日：2000-09-20

申请人： Kazuyuki Nakagawa ,  Michitaka Kimura ,  Masatoshi Yasunaga

发明人： Kazuyuki Nakagawa ,  Michitaka Kimura ,  Masatoshi Yasunaga

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48 ,  H01L23/28 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3114 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device, a semiconductor element is bonded to an insulating circuit board. A resin layer for bonding the semiconductor element to the insulating circuit board is extended so as to become greater in size than the semiconductor element. Further, the surroundings of the semiconductor element are sealed with resin. Reliability of mounting is improved by alleviating stress developing in a solder joint of the external electrodes of the circuit board.

摘要翻译： 在半导体器件中，将半导体元件接合到绝缘电路板。 用于将半导体元件接合到绝缘电路板的树脂层被延伸以使其尺寸变得比半导体元件大。 此外，半导体元件的周围用树脂密封。 通过减轻电路板的外部电极的焊点中的应力显现来提高安装的可靠性。

公开(公告)号：US08605277B2

公开(公告)日：2013-12-10

申请号：US13244434

申请日：2011-09-24

申请人： Satoshi Yamada ,  Takashi Karashima ,  Kenya Hironaga ,  Masatoshi Yasunaga ,  Yuji Fujimoto

发明人： Satoshi Yamada ,  Takashi Karashima ,  Kenya Hironaga ,  Masatoshi Yasunaga ,  Yuji Fujimoto

IPC分类号： G01N21/00

CPC分类号： G01N21/95684 ,  G01B11/306 ,  G01N21/93 ,  H01L23/3128 ,  H01L2224/48227 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00

摘要： Reliability of a semiconductor device is improved. In a flatness inspection of BGA (semiconductor device), there is formed a flatness standard where a permissible range in the direction of (+) of flatness at normal temperature is smaller than a permissible range in the direction of (−). With use of the above flatness standard, a flatness inspection of the semiconductor device at normal temperature is performed to determine whether the mounted item is non-defective or defective. With the above process, defective mounting caused by a package warp when heated during reflow soldering etc. is reduced and reliability of BGA is improved. At the same time, flatness management of a substrate-type semiconductor device with better consideration of a mounting state can be performed.

摘要翻译： 提高了半导体器件的可靠性。 在BGA（半导体器件）的平坦度检查中，形成了平坦度标准，其中常温平面度（+）方向上的允许范围小于（ - ）方向的允许范围。 使用上述平面度标准，进行半导体器件在常温下的平坦度检查，以确定安装的物品是否是有缺陷的或有缺陷的。 通过上述处理，在回流焊接等期间加热时由包装翘曲引起的安装不良导致BGA的可靠性提高。 同时，可以进行更好地考虑安装状态的基板型半导体器件的平坦度管理。

公开(公告)号：US06469395B1

公开(公告)日：2002-10-22

申请号：US09567009

申请日：2000-05-09

申请人： Tatsuto Nishihara ,  Masatoshi Yasunaga

发明人： Tatsuto Nishihara ,  Masatoshi Yasunaga

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device has a first semiconductor chip 2a, a wiring substrate 1 connected to the first semiconductor chip 2a, a first surrounding substrate 6a which has an opening at a position avoiding the first semiconductor chip 2a and which is connected onto the wiring substrate 1 by flip-chip bonding, and a second semiconductor chip 2b connected onto the first surrounding substrate 2a by flip-chip bonding. A second surrounding substrate 6b comprising a two or more number of substrate elements is used for the first surrounding substrate 6a.

摘要翻译： 半导体器件具有第一半导体芯片2a，连接到第一半导体芯片2a的布线基板1，第一周围基板6a，其在避开第一半导体芯片2a的位置处具有开口，并且通过以下方式连接到布线基板1上 倒装芯片接合以及通过倒装芯片接合连接到第一周围基板2a上的第二半导体芯片2b。 包括两个或多个基板元件的第二周围基板6b用于第一周围基板6a。

公开(公告)号：US5075240A

公开(公告)日：1991-12-24

申请号：US509850

申请日：1990-04-17

申请人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

发明人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/266 ,  Y10S438/972

摘要： A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

摘要翻译： 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。

公开(公告)号：US20120061850A1

公开(公告)日：2012-03-15

申请号：US13231856

申请日：2011-09-13

申请人： Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

发明人： Soshi KURODA ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

摘要： To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

摘要翻译： 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US5096853A

公开(公告)日：1992-03-17

申请号：US664119

申请日：1991-03-04

申请人： Masatoshi Yasunaga ,  Masanobu Kohara

发明人： Masatoshi Yasunaga ,  Masanobu Kohara

IPC分类号： H01L21/56 ,  H01L23/495

CPC分类号： H01L21/565 ,  H01L23/49503 ,  H01L24/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49121

摘要： A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding a molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold and solidifying the resin.