公开(公告)号：EP1117283B1

公开(公告)日：2006-05-10

申请号：EP99943326.1

申请日：1999-09-14

Applicant: IBIDEN CO., LTD.

Inventor： EN, Honchin ,  NAKAI, Tohru ,  OKI, Takeo ,  HIROSE, Naohiro ,  NODA, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a printed wiring board having a high-density wiring and a highly-reliable connection between conductor layers even if the annealing process is omitted because a conductor circuit made of an electroplating layer excellent in crystallinity and uniform electrodepositability and formed on a base sheet and a via hole are provided. The method comprising forming an interlayer resin insulating layer on a conductor wiring forming board, making an opening for making a via hole in the interlayer resin insulating layer, forming an electroless plating layer (1008) on the interlayer resin insulating layer, applying a resist film (1003) to the layer (1008), forming an electroplating film thereon, removing the resist film, and removing the electroless plating layer by etching so as to form a conductor wiring and a via hole characterized in that the electroless plating layer (1008) serves as a cathode, the plating metal serves as an anode, and electroplating is performed intermittently while maintaining the voltage between the anode and cathode at a constant value.

Abstract translation: 即使省略退火处理，由于由结晶性和电沉积性均匀性优异的电镀层构成的导体电路形成于基体上，因此即使省略退火处理，也能够提供具有高密度布线和导体层间的可靠性高的连接的印刷布线板的制造方法 薄片和通孔。 该方法包括：在导体布线形成板上形成层间树脂绝缘层，在层间树脂绝缘层上形成用于形成通孔的开口，在层间树脂绝缘层上形成化学镀层（1008），将抗蚀剂膜 （1008），在其上形成电镀膜，去除抗蚀剂膜，并且通过蚀刻除去化学镀层，从而形成导体布线和通孔，其特征在于，无电镀层（1008） 用作阴极，电镀金属用作阳极，并且在将阳极和阴极之间的电压保持在恒定值的同时间歇地执行电镀。

公开(公告)号：EP1653792A1

公开(公告)日：2006-05-03

申请号：EP05108243.6

申请日：2005-09-08

Applicant: ROBERT BOSCH GMBH

Inventor： Gottwald, Frank

IPC: H05K9/00 ,  H05K1/02

CPC classification number: H05K1/0218 ,  H05K3/107 ,  H05K9/0039 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09981 ,  H05K2201/10371

Abstract: Vorrichtung zur Abschirmung elektrischer Schaltungen (7) auf einer Leiterplatte (1) und Verfahren zur Herstellung dieser Vorrichtung, indem ein elektrisch leitfähiger, wannenförmiger Abschirmdeckel (2) mit einer Leiterplatte (1) derart verbunden wird, dass der elektrisch leitfähige, wannenförmige Abschirmdeckel und die Leiterplatte eine elektrische Schaltung einschließen, wobei die Leiterplatte an der Befestigungsfläche, an der diese mit dem Abschirmdeckel verbunden ist, vertieft ist.

Abstract translation: 该装置具有在电学上，导电槽状的屏蔽盖（2）没有与印刷电路板（1）在寻求的方式并在盖连接，并且板包住在电电路（7）。 该板在其中板与盖相连的固定表面凹陷。 板具有与铜套（3），并在面对所述盖的一侧上的层的铜层的矩形，沟槽形状的凹部。 因此独立claimsoft被包括用于在电路制造用于屏蔽的方法。

公开(公告)号：EP1194024B1

公开(公告)日：2006-04-19

申请号：EP99919569.6

申请日：1999-05-13

Applicant: IBIDEN CO., LTD.

Inventor： ASAI, Motoo Ibiden Co., Ltd. ,  NODA, Kouta Ibiden Co., Ltd. ,  KARIYA, Takashi c/o Ibiden Co., Ltd

IPC: H05K3/46

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/421 ,  H05K2201/0195 ,  H05K2201/09509 ,  Y10T428/24273

Abstract: A technique for manufacturing a printed-circuit board by semi-additive method that provides superior adhesion between electroless plating film (12) and electrolytic plating film (13) which compose a conductor circuit (5) without causing separation of plating resist (3). A conductor circuit is formed on a rough surface of an insulating layer (2) of a printed-circuit board. The conductor circuit includes an electroless plating film on the insulator side and an electrolytic plating film on the other side. The electroless plating film is in intimate contact with the rough surface of the insulating layer. The printed-circuit board is manufactured by a semi-additive method in which electroless plating film is formed so that it may make intimate contact with a rough surface of an insulating layer.

公开(公告)号：EP1102525A4

公开(公告)日：2005-10-26

申请号：EP99929729

申请日：1999-07-07

Applicant: IBIDEN CO LTD

Inventor： TSUKADA KIYOTAKA ,  TAKADA MASARU ,  CHIHARA KENJI

IPC: H01L21/48 ,  H01L23/12 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed wiring board and method for producing the same, in which an upper-surface pattern is readily formed, and a lower-surface metal foil is hardly damaged when a blind via hole is made by a laser beam. A lower-surface metal foil (220) is provided over the lower surface of an insulating sheet (5), and an upper-surface metal foil (210) thinner than the lower-surface metal foil (220) is provided over its upper surface. An open hole (213) is made in the upper-surface metal foil in a position corresponding to the area (35) where a blind via hole is formed. A laser beam (8) is projected onto the area (35) through the open hole (213) to make a blind via hole (3) the bottom of which is the lower-surface metal foil. A metal plating film (23) is formed on the inner wall of the blind via hole (3). Upper- and lower-surface patterns (21, 22) are formed by etching.

Abstract translation: 提供一种印刷电路板及其制造方法，其在形成具有激光的盲孔时有利于形成上表面图案并防止下表面金属箔被损坏。 绝缘基板（5）的下表面和上表面分别涂覆有下表面金属箔（220）和上表面金属箔（210），其厚度小于下表面金属箔的厚度 （220）。 接下来，在上表面金属箔的与绝缘基板的盲通孔形成部（35）对应的位置形成开口（213）。 通过开口（213）向盲通孔形成部分（35）发射激光（8），形成其底部为下表面金属箔的盲通孔（3）。 然后，将金属镀膜（23）施加到盲孔（3）的壁上，通过蚀刻形成上表面图案（21）和下表面图案（22）。

公开(公告)号：EP1505860A1

公开(公告)日：2005-02-09

申请号：EP04018473.1

申请日：2004-08-04

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Yatsu, Hiroyuki, Alps Electric Co.Ltd

IPC: H05K5/00 ,  H05K5/03

CPC classification number: H05K3/403 ,  H01L23/055 ,  H01L23/10 ,  H01L24/97 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/0052 ,  H05K3/3405 ,  H05K2201/09181 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10371

Abstract: The present invention provides an electronic circuit module having a certainty of soldering attachment to a motherboard, a small size and a highly reliable connection to the motherboard. An electronic circuit module of the present invention comprises a circuit board (1) formed with laminated plurality of insulating sheets, and a cover (9) made from a metal plate and having attaching legs (9c) soldered to electrode portions (8) in the concave portions (1c) in a state of covering the electronic component (7). The concave portions (1c) are formed from an upper surface of the circuit board (1) toward a lower surface side, stopping portions (1d) for plugging the lower portions of the concave portions (1c) are provided in the circuit board (1), and the attaching legs (9c) of the cover (9) are soldered to the electrode portions (8) in a state of being inserted into the concave portions (1c). As a result, it is possible to prevent the soldering connecting the attaching legs (9c) to the electrode portions (8) from leaking downward by way of the stopping portions (1d). Accordingly, the degree of flatness of the circuit board (1) to the motherboard (10) becomes better and the soldering is reliable.

Abstract translation: 本发明提供一种电子电路模块，其具有焊接附着到主板的可靠性，与主板的小尺寸和高度可靠的连接。 本发明的电子电路模块包括形成有层压的多个绝缘片的电路板（1）和由金属板制成并具有焊接到电极部分（8）的连接脚（9c）的盖（9） 处于覆盖电子部件（7）的状态的凹部（1c）。 凹部（1c）由电路基板（1）的上表面朝向下表面侧形成，用于堵塞凹部（1c）的下部的停止部（1d）设置在电路基板（1） ），并且在插入凹部（1c）的状态下，将盖（9）的安装腿（9c）焊接到电极部（8）。 结果，可以防止通过停止部（1d）将连接脚（9c）与电极部（8）的焊接部向下泄漏。 因此，电路板（1）与母板（10）的平坦度变得更好，焊接可靠。

公开(公告)号：EP1408520A3

公开(公告)日：2005-02-09

申请号：EP03022085.9

申请日：2003-10-02

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J.

IPC: H01G4/30 ,  H01G4/33 ,  H01G9/04

CPC classification number: H01G4/01 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  Y10T29/4913

Abstract: A capacitor structure (100) is fabricated by forming a pattern of first dielectrics (120,125) over a foil (110), forming first electrodes (130) over the first dielectrics (120,125), and co-firing the first dielectrics and the first electrodes (130). Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.

公开(公告)号：EP1498944A1

公开(公告)日：2005-01-19

申请号：EP04253875.1

申请日：2004-06-29

Applicant: E.I. du Pont de Nemours and Company ,  North Carolina State University

Inventor： Borland, William J. ,  Ihlefeld, Jon Frederick ,  Kingon, Angus Ian ,  Maria, Jon-Paul

IPC: H01L21/70 ,  H05K1/16 ,  H01G4/33 ,  H01G4/10 ,  H01G4/12

CPC classification number: H05K1/162 ,  H01G4/1218 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/125

Abstract: The invention provides a method of making a capacitor, comprising:
providing a metallic foil; forming a dielectric layer over the foil;
annealing the dielectric layer; re-oxygenating the dielectric resulting from the annealing; and forming a conductive layer over the dielectric. The capacitors are suitable for use on printed wiring boards.

Abstract translation: 本发明提供一种制造电容器的方法，包括：提供金属箔; 在所述箔上形成介电层; 退火介电层; 对由退火产生的电介质进行再充氧; 并在电介质上形成导电层。 这些电容适用于印刷电路板。

公开(公告)号：EP1473977A2

公开(公告)日：2004-11-03

申请号：EP04250754.1

申请日：2004-02-12

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Alcoe, David

IPC: H05K1/11 ,  H01L23/498 ,  H01L23/485

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318

Abstract: An electronic package and information handling system utilizing same wherein the package substrate (11') includes an internally conductive layer (15') coupled to an external pad (13') and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.

Abstract translation: 一种利用其的电子封装和信息处理系统，其中封装衬底（11'）包括耦合到外部焊盘（13'）的内部导电层（15'），其尺寸足够大以基本上防止开裂，分离等 当垫受到约1.4克/平方密度或更大的拉伸压力时，

公开(公告)号：EP1461985A2

公开(公告)日：2004-09-29

申请号：EP03789847.5

申请日：2003-11-20

Applicant: Nortel Networks Limited

Inventor： KWONG, Herman ,  DIFILIPPO, Luigi ,  DUXBURY, Guy ,  MARCANTI, Larry

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/023 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A technique for accommodating electronic components on a multilayer signal routing device (100) is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for accommodating electronic components on a multilayer signal routing device (100). Such a method comprises determining a component space that is required to accommodate a plurality of electronic components on a surface of a multilayer signal routing device (100), and then forming at least one signal routing channel (104) on at least the surface of the multilayer signal routing device (100), wherein the at least one signal routing channel (104) has a channel space that is equal to or greater than the component space.

公开(公告)号：EP1434473A3

公开(公告)日：2004-08-04

申请号：EP03394085.9

申请日：2003-09-12

Applicant: Nortel Networks Limited

Inventor： Duxbury, Guy A. ,  Kwong, Herman ,  Wyrzykowska, Aneta ,  Difilippo, Luigi G.

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/498

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A technique for reducing the number of layers in a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing the number of layers in a multilayer signal routing device (10) having a plurality of electrically conductive signal path layers (16) for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer signal routing device (10). In such a case, the method comprises routing electrical signals on the plurality of electrically conductive signal path layers (16) in the multilayer signal routing device (10) for connection to and from a high density electrically conductive contact array package based at least in part upon at least one of an electrically conductive contact signal type characteristic and an electrically conductive contact signal direction characteristic.