公开(公告)号：US20190202136A1

公开(公告)日：2019-07-04

申请号：US15859318

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Mark SALTAS ,  Amram EITAN

IPC: B29C65/48 ,  B29C65/02 ,  C09J9/02 ,  C09J163/00 ,  C09J175/04 ,  C09J5/06 ,  H05K1/18 ,  H05K3/32

CPC classification number: B29C65/4805 ,  B29C65/02 ,  B29L2031/3425 ,  C08K3/02 ,  C08K3/04 ,  C08K2003/023 ,  C08K2003/0806 ,  C08K2003/0812 ,  C08K2201/001 ,  C09J5/06 ,  C09J9/02 ,  C09J163/00 ,  C09J175/04 ,  C09J2205/31 ,  C09J2400/10 ,  C09J2400/16 ,  C09J2463/00 ,  C09J2475/00 ,  H05K1/181 ,  H05K3/321 ,  H05K2201/0215 ,  H05K2203/166

Abstract: Apparatuses, systems and methods associated with procedures and adhesive elements for affixing components together are disclosed herein. In embodiments, an assembly may include a first component and a second component coupled to the first component. The assembly may further include a plurality of adhesive elements located between the first component and the second component, wherein the plurality of adhesive elements couple the second component to the first component, and wherein each adhesive element of the plurality of adhesive elements is equidistance from adjacent adhesive elements of the plurality of adhesive elements. Other embodiments may be described and/or claimed.

公开(公告)号：US20210066155A1

公开(公告)日：2021-03-04

申请号：US16557784

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20190206821A1

公开(公告)日：2019-07-04

申请号：US15859313

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Huxiao XIE ,  Amram EITAN ,  Xiao LU

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10165 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/13211 ,  H01L2224/13311 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13411 ,  H01L2224/13499 ,  H01L2224/16237 ,  H01L2224/165 ,  H01L2224/80051 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

公开(公告)号：US20240014097A1

公开(公告)日：2024-01-11

申请号：US18372542

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/373 ,  H01L21/565 ,  H01L23/481 ,  H01L21/02288 ,  H01L21/76816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20170154828A1

公开(公告)日：2017-06-01

申请号：US14953779

申请日：2015-11-30

Applicant: INTEL CORPORATION

Inventor： Timothy A. GOSSELIN ,  Patrick NARDI ,  Kartik SRINIVASAN ,  Amram EITAN ,  Ji Yong PARK ,  Christopher L. RUMER ,  George S. KOSTIEW

IPC: H01L21/66 ,  B23K20/02 ,  B23K20/00 ,  H01L23/00

CPC classification number: H01L22/12 ,  B23K1/0016 ,  B23K20/002 ,  B23K20/026 ,  B23K20/16 ,  B23K20/233 ,  B23K20/24 ,  B23K20/26 ,  B23K31/12 ,  B23K2101/42 ,  H01L22/20 ,  H01L24/14 ,  H01L24/75 ,  H01L2224/81192 ,  H01L2924/351

Abstract: A method and machine-readable medium including non-transitory program instructions that when executed by a processor cause the processor to perform a method including measuring at least one parameter of a substrate or a die; and establishing or modifying a thermal compression bonding recipe based on the at least one parameter, wherein the thermal compression bonding recipe is operable for thermal compression bonding of the die and the substrate. A thermal compression bonding tool including a pedestal operable to hold a substrate during a thermal compression bonding process and a bond head operable to engage a die, the tool including a controller machine readable instructions to process a substrate and a die combination, the instructions including an algorithm to implement or modify a thermal compression bonding process based on a parameter of a substrate or die.

公开(公告)号：US20240128152A1

公开(公告)日：2024-04-18

申请号：US18399205

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/02288 ,  H01L21/565 ,  H01L21/76816 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240021493A1

公开(公告)日：2024-01-18

申请号：US18374587

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/76816 ,  H01L21/565 ,  H01L21/02288 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20180358296A1

公开(公告)日：2018-12-13

申请号：US15778398

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Eric J. LI ,  Nitin DESHPANDE ,  Shawna M. LIFF ,  Omkar KARHADE ,  Amram EITAN ,  Timothy A. GOSSELIN

IPC: H01L23/538 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.