公开(公告)号：US20240006283A1

公开(公告)日：2024-01-04

申请号：US17853487

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattawa NAD ,  Rahul N. MANEPALLI ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Yi YANG ,  Marcel WALL ,  Darko GRUJICIC ,  Haobo CHEN ,  Aaron GARELICK

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.

公开(公告)号：US20230090350A1

公开(公告)日：2023-03-23

申请号：US17478439

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Kyle MCELHINNY ,  Haobo CHEN ,  Hongxia FENG ,  Xiaoying GUO ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

公开(公告)号：US20220310518A1

公开(公告)日：2022-09-29

申请号：US17213147

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Haobo CHEN ,  Xiaoying GUO ,  Hongxia FENG ,  Kristof DARMAWIKARTA ,  Bai NIE ,  Tarek A. IBRAHIM ,  Gang DUAN ,  Jeremy D. ECTON ,  Sheng C. LI ,  Leonel ARANA

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20250113434A1

公开(公告)日：2025-04-03

申请号：US18374617

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Bai NIE ,  Mitchell PAGE ,  Junxin WANG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Haifa HARIRI ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Hongxia FENG ,  Haobo CHEN ,  Bohan SHAN ,  Hiroki TANAKA ,  Leonel R. ARANA ,  Yonggang Yong LI

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20240105571A1

公开(公告)日：2024-03-28

申请号：US17954288

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Haobo CHEN ,  Bai NIE ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.