-
公开(公告)号:US10991676B2
公开(公告)日:2021-04-27
申请号:US16814175
申请日:2020-03-10
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Javier A. Delacruz
IPC: H01L21/78 , H01L25/065 , H01L23/00 , H01L25/00
Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
-
公开(公告)号:US10802285B2
公开(公告)日:2020-10-13
申请号:US16292705
申请日:2019-03-05
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Rajesh Katkar
Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
-
公开(公告)号:US10593563B2
公开(公告)日:2020-03-17
申请号:US15873218
申请日:2018-01-17
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Rajesh Katkar
IPC: H01L21/48 , H01L21/56 , H01L21/78 , H01L23/538 , H01L25/10 , H01L23/00 , H01L23/498 , H01L21/683 , H01L23/31
Abstract: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.
-
公开(公告)号:US10290612B1
公开(公告)日:2019-05-14
申请号:US15993271
申请日:2018-05-30
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Ilyas Mohammed , Javier A. Delacruz
IPC: H01L23/544 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/78
Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
-
公开(公告)号:US10015881B2
公开(公告)日:2018-07-03
申请号:US14573461
申请日:2014-12-17
Applicant: Invensas Corporation
Inventor: Cyprian Emeka Uzoh , Craig Mitchell , Belgacem Haba , Ilyas Mohammed
CPC classification number: H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
Abstract: A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.
-
公开(公告)号:US09917073B2
公开(公告)日:2018-03-13
申请号:US15196635
申请日:2016-06-29
Applicant: Invensas Corporation
Inventor: Ilyas Mohammed
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/498 , H01L25/10 , H01L25/18 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/49811 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/91 , H01L24/92 , H01L25/105 , H01L25/18 , H01L2224/0233 , H01L2224/02371 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/24011 , H01L2224/24147 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/73217 , H01L2224/73253 , H01L2224/73259 , H01L2224/73267 , H01L2224/8203 , H01L2224/821 , H01L2224/83855 , H01L2224/9202 , H01L2224/92144 , H01L2225/06548 , H01L2225/06558 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/18161 , H01L2924/18162 , H01L2924/19107 , H01L2924/00014 , H05K3/4661 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.
-
7.
公开(公告)号:US09876002B2
公开(公告)日:2018-01-23
申请号:US15419237
申请日:2017-01-30
Applicant: Invensas Corporation
Inventor: Terrence Caskey , Ilyas Mohammed
IPC: H01L25/00 , H01L25/18 , H01L25/065 , H01L25/10 , H01L23/13 , H01L23/538 , H01L25/11 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/00 , H01L23/498 , H01L21/768
CPC classification number: H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
-
公开(公告)号:US09832887B2
公开(公告)日:2017-11-28
申请号:US13961217
申请日:2013-08-07
Applicant: Invensas Corporation
Inventor: Liang Wang , Ilyas Mohammed , Belgacem Haba
CPC classification number: H05K3/42 , H01L21/486 , H01L23/49811 , H01L23/49827 , H01L2224/16225 , H05K1/0296 , H05K1/11 , Y10T29/49204
Abstract: Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements.
-
公开(公告)号:US09685365B2
公开(公告)日:2017-06-20
申请号:US13962332
申请日:2013-08-08
Applicant: Invensas Corporation
Inventor: Ilyas Mohammed
IPC: H01R43/02 , H01L21/768 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/31
CPC classification number: H01L21/768 , H01L21/4853 , H01L21/4885 , H01L21/56 , H01L23/3121 , H01L23/49811 , H01L2224/0401 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/78301 , H01L2924/19107
Abstract: A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region.
-
公开(公告)号:US20160260671A1
公开(公告)日:2016-09-08
申请号:US15156667
申请日:2016-05-17
Applicant: Invensas Corporation
Inventor: Belgacem Haba , Richard Dewitt Crisp , Wael Zohni , Ilyas Mohammed
IPC: H01L23/538 , H01L25/065
CPC classification number: H01L23/5386 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/525 , H01L23/5384 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2225/0651 , H01L2225/06513 , H01L2225/06548 , H01L2225/06562 , H01L2225/06572 , H01L2225/1023 , H01L2225/1052 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.
-
-
-
-
-
-
-
-
-