公开(公告)号：US11515229B2

公开(公告)日：2022-11-29

申请号：US16835322

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/52 ,  H01L25/00

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US11469218B2

公开(公告)日：2022-10-11

申请号：US17073888

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US11302600B2

公开(公告)日：2022-04-12

申请号：US16718211

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/42

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

公开(公告)号：US20200343193A1

公开(公告)日：2020-10-29

申请号：US16927126

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

公开(公告)号：US10700033B2

公开(公告)日：2020-06-30

申请号：US16101871

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Bor-Rung Su

IPC: H01L23/00 ,  H01L23/482 ,  H01L23/498 ,  H01L21/56 ,  H01L21/768 ,  H01L21/28 ,  H01L23/538 ,  H01L21/302 ,  H01L23/48

Abstract: The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.

公开(公告)号：US09941216B2

公开(公告)日：2018-04-10

申请号：US15281043

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yen Chiu ,  Ching-Fu Chang ,  Chien-Chia Chiu ,  Hsin-Chieh Huang ,  Tsung-Shu Lin ,  Pei-Ti Yu

IPC: H01L23/538 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.

公开(公告)号：US11901320B2

公开(公告)日：2024-02-13

申请号：US18064371

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L21/76 ,  H01L21/56 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L21/76885 ,  H01L23/3185 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/06515 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81805 ,  H01L2224/83005 ,  H01L2224/838 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/18 ,  H01L2924/0001

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US20230386908A1

公开(公告)日：2023-11-30

申请号：US17819341

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Tsung-Shu Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76829 ,  H01L21/76807 ,  H01L24/03 ,  H01L2224/03011 ,  H01L2224/02235 ,  H01L2224/02251 ,  H01L2924/35 ,  H01L2224/06179 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L24/06

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.

公开(公告)号：US20230369162A1

公开(公告)日：2023-11-16

申请号：US18361332

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Tsung-Yu Chen ,  Tsung-Shu Lin ,  Chen-Hsiang Lao ,  Wen-Hsin Wei ,  Hsien-Pin Hu

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/67 ,  H01L23/40

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/4878 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0655 ,  H01L21/67092 ,  H01L23/40 ,  H01L2224/16225

Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.

公开(公告)号：US20230144244A1

公开(公告)日：2023-05-11

申请号：US18153532

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC: H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/427 ,  H01L21/4882 ,  H01L25/50 ,  H01L25/0655

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.