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    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR
    92.
    发明申请
    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR 有权
    包含电路的集成电路用于确定注射锁定振荡器的设置

    公开(公告)号：US20150333760A1

    公开(公告)日：2015-11-19

    申请号：US14651571

    申请日：2014-01-03

    Applicant: RAMBUS INC.

    Inventor： Jared L. Zerbe ,  Masum Hossain

    IPC: H03L7/24 ,  H03L7/06 ,  H03L1/00

    CPC classification number: H03L7/24 ,  H03K3/0307 ,  H03K3/0315 ,  H03L1/00 ,  H03L7/06

    Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

    Abstract translation: 描述了包括用于确定注入锁定振荡器（ILO）的设置的电路的集成电路（IC）的实施例。 在一些实施例中，基于参考时钟信号的第一时钟沿产生注入信号，并将其注入国际劳工组织。 接下来，基于参考时钟信号的第二时钟沿对ILO的一个或多个输出信号进行采样，并且基于样本确定ILO的设置。 在一些实施例中，基于参考时钟信号和自由运行的ILO生成两个或更多个时间数字（TDC）码的序列。 在一些实施例中，已经存在于延迟锁定环路中的TDC电路被重新用于确定两个或多个TDC码的序列。 然后可以基于两个或多个TDC代码的顺序来确定ILO设置。

    Selectable-tap Equalizer
    95.
    发明申请
    Selectable-tap Equalizer 有权
    可选择点击均衡器

    公开(公告)号：US20150180646A1

    公开(公告)日：2015-06-25

    申请号：US14616629

    申请日：2015-02-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

    CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    Abstract translation: 一种具有可选择抽头均衡器的信令电路。 信令电路包括缓冲器，选择电路和均衡电路。 缓冲器用于存储对应于在第一时间间隔期间在信令路径上发送的数据信号的多个数据值。 选择电路耦合到缓冲器，以根据选择值从多个数据值中选择数据值的子集。 均衡电路被耦合以从选择电路接收数据值的子集，并且适于根据数据值的子集来调整对应于在第二时间间隔期间在信令路径上发送的数据信号的信号电平。

    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
    96.
    发明申请
    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 有权
    低功率源同步信号

    公开(公告)号：US20140334236A1

    公开(公告)日：2014-11-13

    申请号：US14445014

    申请日：2014-07-28

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Frederick A. Ware

    IPC: G11C11/4076

    CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

    Abstract translation: 公开了一种操作存储器控制器的方法。 该方法包括通过至少两个并行数据链路中的每一个将数据信号发送到存储器设备。 在第一专用链路上将定时信号发送到存储设备。 定时信号与数据信号具有固定的相位关系。 数据选通信号被驱动到第二专用链路上的存储器件。 从存储器件接收相位信息。 相位信息在存储器件内部产生，并且基于定时信号与内部分布在存储器件内的数据选通信号的版本之间的比较。 基于接收的相位信息，相对于定时信号调整数据选通信号的相位。

    SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTS
    98.
    发明申请
    SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTS 审中-公开
    信号线路径降低CROSSTALK效应

    公开(公告)号：US20130322510A1

    公开(公告)日：2013-12-05

    申请号：US13893229

    申请日：2013-05-13

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe

    IPC: H04B3/32

    CPC classification number: H04B3/32 ,  H01R13/6467 ,  H05K1/0228 ,  H05K2201/09245 ,  H05K2201/10689

    Abstract: A signaling system is disclosed. The system includes a transmitter comprising an encoder to encode a data signal such that the encoded data signal has a balanced number of logical 1s and 0s. The system also includes a receiver having a decoder to decode the encoded data signal, and a link. The link is coupled between the transmitter and the receiver to route the encoded data signal. The link comprises three or more conductive lines that are routed along a path in parallel between the encoder and the decoder, and wherein the link comprises segments, each segment comprising a routing change to reorder proximity of at least one pair of lines relative to any adjacent segment, with a sufficient number of segments such that each line has each of the other lines of the link as a nearest neighbor over at least a portion of the path.

    Abstract translation: 公开了一种信令系统。 该系统包括发射机，包括编码器，用于对数据信号进行编码，使得编码数据信号具有平衡数量的逻辑1和0。 该系统还包括具有用于解码编码数据信号的解码器的接收器和链路。 该链路耦合在发射机和接收机之间以路由编码的数据信号。 该链路包括沿编码器和解码器之间的并行路径路由的三条或更多条导线，并且其中链路包括段，每个段包括路由改变，以重新排列至少一对线相对于任何相邻 段，具有足够数量的段，使得每条线在链路的至少一部分上具有链路的每条其他线路作为最近邻居。

    INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP
    99.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP 审中-公开
    包含延迟环路的集成电路

    公开(公告)号：US20130121094A1

    公开(公告)日：2013-05-16

    申请号：US13676945

    申请日：2012-11-14

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

    IPC: H03L7/091 ,  G11C8/18

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

    Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

    Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

    Split-path equalizer and related methods, devices and systems
    100.
    发明授权
    Split-path equalizer and related methods, devices and systems 有权

    公开(公告)号：US12267187B1

    公开(公告)日：2025-04-01

    申请号：US17901780

    申请日：2022-09-01

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Jared L. Zerbe

    IPC: H04L25/03 ,  H03L7/00 ,  H03L7/08 ,  H04L7/00 ,  H04L7/033 ,  H04L25/08

    Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

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