公开(公告)号：US09343463B2

公开(公告)日：2016-05-17

申请号：US12586900

申请日：2009-09-29

Applicant: Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

Inventor： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

IPC: H01L29/66 ,  H01L21/4763 ,  H01L27/105 ,  H01L21/768 ,  H01L23/522 ,  H01L27/22

CPC classification number: H01L27/105 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/522 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract translation: 集成CMOS级别和有源器件级别的结构和方法可以是存储器件级。 整合包括通过使用两个单独的图案化和蚀刻工艺对完整的有源和虚拟互连通孔进行图案化形成的两层之间形成“超平面”界面。 有源通孔将上部器件电平的存储器件连接到较低CMOS电平的连接焊盘。 虚拟通孔可以延伸到在CMOS层上形成的蚀刻停止层，或者可以在形成在器件级内的中间蚀刻停止层处停止。 因此，虚拟通孔接触存储器件，但不将它们连接到CMOS电平中的有源元件。

公开(公告)号：US09343452B2

公开(公告)日：2016-05-17

申请号：US14542709

申请日：2014-11-17

Applicant: Tae-Hwan Yun ,  Jin-Taek Park

Inventor： Tae-Hwan Yun ,  Jin-Taek Park

IPC: H01L27/02 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L23/49517 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/105 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.

Abstract translation: 半导体器件包括具有单元区域和连接区域的衬底。 多个栅电极在基板的单元区域中沿垂直方向堆叠。 电连接到外围电路的导电焊盘从栅电极向连接区水平延伸。 导电焊盘在连接区域中形成级联结构。 具有不同垂直长度的接触塞电连接到相应的导电焊盘。 导电焊盘具有在垂直方向上比栅电极更厚的接触部分。

公开(公告)号：US20160133636A1

公开(公告)日：2016-05-12

申请号：US14980147

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu

IPC: H01L27/115 ,  H01L21/321 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1116 ,  H01L27/11546 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/66545

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract translation: 嵌入式闪速存储器件包括栅堆叠，其包括延伸到半导体衬底中的凹部中的底部电介质层和位于底部电介质层上的电荷存储层。 电荷存储层包括凹部中的一部分。 栅极堆叠还包括电荷存储层上的顶部电介质层，以及在顶部电介质层上方的金属栅极。 源极和漏极区位于半导体衬底中，并且位于栅堆叠的相对侧上。

公开(公告)号：US09312269B2

公开(公告)日：2016-04-12

申请号：US14272853

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/108 ,  G11C11/00 ,  H01L27/105 ,  G11C14/00 ,  H01L27/11

CPC classification number: H01L27/11563 ,  G11C11/005 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/10894 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

Abstract translation: 具有新型结构的半导体器件，其中提供了即使使用小型化元件来保持数据所需的存储容量。 在半导体器件中，电容器的电极是设置在与晶体管的栅极相同的层中的电极和设置在与晶体管的源极和漏极相同的层中的电极。 此外，在不同的层中设置提供晶体管的栅极的层和连接多个存储器中的晶体管的栅极的布线层。 利用这种结构，可以减小在晶体管的栅极周围形成的寄生电容，并且可以在更大的面积中形成电容器。

公开(公告)号：US20160079983A1

公开(公告)日：2016-03-17

申请号：US14842195

申请日：2015-09-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Shinichi YASUDA

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  B82Y10/00 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L23/5252 ,  H01L24/45 ,  H01L25/0655 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/2463 ,  H01L2924/00014 ,  H01L2924/13091 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/356182 ,  H03K17/223 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: According to one embodiment, a reconfigurable circuit includes first, second, third and fourth circuit blocks arranged with a matrix, a first conductive line shared by the first and second circuit blocks, a second conductive line shared by the third and fourth circuit blocks, a third conductive line shared by the first and third circuit blocks, the third conductive line crossing the first and second conductive lines, a fourth conductive line shared by the second and fourth circuit blocks, the fourth conductive line crossing the first and second conductive lines, a first controller controlling voltages to be applied to the first and second conductive lines, and a second controller controlling voltages to be applied to the third and fourth conductive lines.

Abstract translation: 根据一个实施例，可重构电路包括布置有矩阵的第一，第二，第三和第四电路块，由第一和第二电路块共享的第一导线，由第三和第四电路块共享的第二导线， 由第一和第三电路块共享的第三导线，与第一和第二导线交叉的第三导线，由第二和第四电路块共享的第四导线，与第一和第二导线交叉的第四导线， 控制施加到第一和第二导线的电压的第一控制器，以及控制施加到第三和第四导线的电压的第二控制器。

公开(公告)号：US20160049399A1

公开(公告)日：2016-02-18

申请号：US14865784

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28026 ,  H01L21/2807 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/105 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/772 ,  H01L29/7833 ,  H01L29/785

Abstract: One illustrative gate structure of a transistor device disclosed herein includes a high-k gate insulation layer and a work function metal layer positioned on the high-k gate insulation layer. The device further includes a first bulk metal layer positioned on the work function metal layer. The device further includes a second bulk metal layer. The first and second bulk metal layers have upper surfaces that are at substantially the same height level, and the first and second bulk metal layers are made of substantially the same material. The device further includes a conductive etch stop layer between the first and second bulk metal layers.

Abstract translation: 本文公开的晶体管器件的一个说明性栅极结构包括高k栅极绝缘层和位于高k栅极绝缘层上的功函数金属层。 该装置还包括位于功函数金属层上的第一体金属层。 该装置还包括第二体金属层。 第一和第二块体金属层具有基本上相同的高度水平的上表面，并且第一和第二块体金属层由基本上相同的材料制成。 该器件还包括在第一和第二块体金属层之间的导电蚀刻停止层。

公开(公告)号：US09263450B2

公开(公告)日：2016-02-16

申请号：US13715119

申请日：2012-12-14

Applicant: Magnachip Semiconductor, Ltd.

Inventor： Seong-do Jeon

IPC: H01L27/105 ,  H01L21/762 ,  H01L27/112 ,  G11C17/16

CPC classification number: H01L21/76224 ,  G11C17/16 ,  H01L27/105 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238

Abstract: A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.

公开(公告)号：US20160043138A1

公开(公告)日：2016-02-11

申请号：US14882183

申请日：2015-10-13

Applicant: SK hynix Inc.

Inventor： Jae-Yun YI

IPC: H01L27/24 ,  H01L29/786 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/24 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

Abstract: A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

Abstract translation: 半导体器件包括具有晶体管区域和存储区域的存储器块。 存储区域的可变电阻层用作晶体管区域中的栅极绝缘层。

公开(公告)号：US09245891B2

公开(公告)日：2016-01-26

申请号：US14072878

申请日：2013-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  H01L27/105 ,  G11C19/28 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/13 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2202/103 ,  G09G3/3266 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/023 ,  G11C19/28 ,  H01L27/105 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/42384 ,  H01L29/78663 ,  H01L29/78678 ,  H01L29/78696

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract translation: 通过将AC脉冲施加到容易劣化的晶体管的栅极，抑制了晶体管的阈值电压偏移。 然而，在非晶硅用于晶体管的半导体层的情况下，阈值电压偏移的发生自然成为构成产生AC脉冲的电路的一部分的晶体管的问题。 容易劣化的晶体管的阈值电压偏移和导通晶体管的阈值电压偏移被信号输入到通过导通晶体管容易劣化的晶体管的栅电极而被抑制。 换句话说，包括将AC脉冲施加到通过晶体管容易劣化到施加了高电位（VDD）的栅电极的晶体管的栅电极的结构。

公开(公告)号：US09236383B2

公开(公告)日：2016-01-12

申请号：US11495499

申请日：2006-07-28

Applicant: H. Montgomery Manning

Inventor： H. Montgomery Manning

IPC: H01L21/311 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/105 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/1104

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.