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公开(公告)号：US20150053463A1
公开(公告)日：2015-02-26
申请号：US14093660
申请日：2013-12-02
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： CHI-SHIANG CHEN , HSIU-CHING HU , KUN-WU LI , FANG-PING WU
CPC classification number: H05K3/4691 , H05K1/0278 , H05K1/185 , H05K3/0011 , H05K3/0035 , H05K3/0047 , H05K3/005 , H05K3/007 , H05K3/4644 , H05K3/4694 , H05K2201/048 , H05K2203/0384 , H05K2203/167 , Y10T29/49155
Abstract: A rigid flex board module includes a rigid flex circuit board and a high-density interconnected circuit board. The rigid flex circuit board includes a flexible circuit board, a first rigid circuit board and a first adhesive layer. The flexible circuit board includes a bending portion and a jointing portion connected to the bending part. The rigid flex circuit board is disposed on the jointing portion to expose the bending portion. The first rigid circuit board electrically connects with the flexible circuit board. The first adhesive layer connects the first rigid circuit board and the jointing portion. The high-density interconnected circuit board is disposed in the first rigid circuit board and is electrically connected to the first rigid circuit board.
Abstract translation: 刚性柔性板模块包括刚性柔性电路板和高密度互连电路板。 刚性柔性电路板包括柔性电路板，第一刚性电路板和第一粘合剂层。 柔性电路板包括弯曲部和连接到弯曲部的接合部。 刚性柔性电路板设置在接合部分上以露出弯曲部分。 第一刚性电路板与柔性电路板电连接。 第一粘合剂层连接第一刚性电路板和接合部分。 高密度互连电路板设置在第一刚性电路板中并与第一刚性电路板电连接。
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公开(公告)号：US20150053462A1
公开(公告)日：2015-02-26
申请号：US14062912
申请日：2013-10-25
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Wei-Ming Cheng , Hung-Lin Chang
IPC: H05K1/02
CPC classification number: H05K1/0206 , H01L21/568 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/73259 , H05K1/0203 , H05K1/0207 , H05K1/16 , H05K1/185 , H05K3/4602 , H05K2201/0187 , H05K2201/0195 , H05K2201/09527 , H05K2201/10219
Abstract: A wiring board structure adapted to carry a heat generating component is provided. The wiring board structure includes a core layer, an active cooler, a dielectric layer and a plurality of conductive vias. The core layer has a cavity penetrating through the core layer. The active cooler includes a cold surface and a hot surface. The active cooler is disposed in the cavity. The dielectric layer covers the core layer and fills a gap between the active cooler and the cavity. The heat-generating component is disposed on an outer surface of the dielectric layer. The conductive vias are disposed in the dielectric layer and connecting the cold surface and the outer surface to connect the heat-generating component and the active cooler. A wiring board structure having an active cooling via is also provided.
Abstract translation: 提供适于承载发热部件的布线板结构。 布线板结构包括芯层，有源冷却器，电介质层和多个导电通孔。 芯层具有穿透芯层的腔体。 主动冷却器包括冷表面和热表面。 有源冷却器设置在空腔中。 电介质层覆盖芯层并填充主动式冷却器和空腔之间的间隙。 发热部件设置在电介质层的外表面上。 导电通孔设置在电介质层中，并连接冷表面和外表面，以连接发热部件和主动冷却器。 还提供了具有主动冷却通路的布线板结构。
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公开(公告)号：US08955218B2
公开(公告)日：2015-02-17
申请号：US14073846
申请日：2013-11-06
Applicant: Unimicron Technology Corp.
Inventor： Tsung-Yuan Chen , Shih-Lian Cheng
CPC classification number: H05K3/4038 , H01L21/4857 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/83102 , H01L2924/12042 , H01L2924/15311 , H05K3/10 , H05K3/3436 , H05K3/4644 , H05K3/4694 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , H01L2924/014 , H01L2924/00
Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.
Abstract translation: 封装基板包括芯层，第一介电层，第二电路图案，第一焊接掩模和绝缘层。 第一电路图案设置在芯层的第一表面上。 第一电介质层覆盖第一电路图案。 第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。 第一焊接掩模覆盖芯片安装区域外的第二电路图案的一部分。 绝缘层覆盖芯片安装区域和互连电路图案。 多个嵌入式焊盘位于绝缘层的上表面上。
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公开(公告)号：US20140225272A1
公开(公告)日：2014-08-14
申请号：US13762385
申请日：2013-02-08
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Yu-Chen Chuo , Wei-Ming Cheng
IPC: H01L23/552
CPC classification number: H01L23/552 , H01L23/3135 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/82039 , H01L2924/12042 , H01L2924/15153 , H01L2924/00
Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.
Abstract translation: 嵌入式电子器件封装结构包括芯层，电子器件，第一介电层，第二介电层和导电通孔。 芯层具有空腔，与第一表面相对的第一表面和第二表面。 电子设备设置在空腔中。 设置在第一表面上的第一介电层填充在空腔的一部分中并且覆盖电子设备的一侧。 设置在第二表面上的第二电介质层填充在空腔中，覆盖电子器件的另一侧并连接第一电介质层。 第一和第二介电层完全覆盖电子设备。 导电通孔围绕电子器件的周围设置并穿透第一和第二介电层和芯层。 导电通孔分别连接第一和第二介电层。
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公开(公告)号：US08803310B1
公开(公告)日：2014-08-12
申请号：US13762385
申请日：2013-02-08
Applicant: Unimicron Technology Corp.
Inventor： Yu-Chen Chuo , Wei-Ming Cheng
IPC: H01L23/12
CPC classification number: H01L23/552 , H01L23/3135 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/82039 , H01L2924/12042 , H01L2924/15153 , H01L2924/00
Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.
Abstract translation: 嵌入式电子器件封装结构包括芯层，电子器件，第一介电层，第二介电层和导电通孔。 芯层具有空腔，与第一表面相对的第一表面和第二表面。 电子设备设置在空腔中。 设置在第一表面上的第一介电层填充在空腔的一部分中并且覆盖电子设备的一侧。 设置在第二表面上的第二电介质层填充在空腔中，覆盖电子器件的另一侧并连接第一电介质层。 第一和第二介电层完全覆盖电子设备。 导电通孔围绕电子器件的周围设置并穿透第一和第二介电层和芯层。 导电通孔分别连接第一和第二介电层。
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Patent Agency Ranking
公开(公告)号：US20140154463A1
公开(公告)日：2014-06-05
申请号：US13737954
申请日：2013-01-10
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Shun-Hsiang Liang
CPC classification number: H05K3/0032 , B23K26/384 , B23K2101/42 , H05K2201/09854 , H05K2203/1476 , H05K2203/1572 , Y10T428/24273
Abstract: A substrate structure includes an insulation base material and a through hole. The through hole passes through the insulation base material. Besides, the through hole has a first opening, a second opening, and a third opening communicated with one another. The third opening is located between the first opening and the second opening. A first included angle is formed between an inner wall of the first opening and an inner wall of the third opening. A second included angle is formed between an inner wall of the second opening and the inner wall of the third opening. The minimum diameter of the third opening is at the center of the through hole and defines a neck end portion. Diameters of the first opening and the second opening gradually decrease in a direction toward the neck end portion.
Abstract translation: 基板结构包括绝缘基材和通孔。 通孔穿过绝缘基材。 此外，通孔具有彼此连通的第一开口，第二开口和第三开口。 第三开口位于第一开口和第二开口之间。 在第一开口的内壁和第三开口的内壁之间形成第一夹角。 在第二开口的内壁和第三开口的内壁之间形成第二夹角。 第三开口的最小直径位于通孔的中心并且限定颈部端部。 第一开口和第二开口的直径朝向颈端部的方向逐渐减小。
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107.发明申请公开(公告)号：US20140119688A1
公开(公告)日：2014-05-01
申请号：US13776737
申请日：2013-02-26
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Pei-Chang Huang , Wen-Fang Liu , Cheng-Po Yu
CPC classification number: G02B6/12 , G02B6/4214 , G02B6/423 , G02B6/4232 , H05K1/0274 , H05K1/0298 , H05K3/4626 , H05K2201/0187 , H05K2201/10121 , Y10T29/49126
Abstract: A circuit board, a manufacturing method thereof, and an electro-optic apparatus having the circuit board are provided. The circuit board includes a substrate including a first dielectric layer and a first circuit layer disposed thereon, a waveguide layer disposed on a portion of the substrate, a second dielectric layer, a convex structure and a second circuit layer. The second dielectric layer is disposed on the substrate and the waveguide layer. The second dielectric layer has an opening exposing the sidewall of the waveguide layer and a portion of the first circuit layer. The convex structure is disposed on the sidewall of the waveguide layer. The convex structure and the waveguide layer respectively have refractive index n1 and n2, and |n1-n21|n1
Abstract translation: 提供一种电路板及其制造方法以及具有该电路板的电光装置。 电路板包括：基板，包括第一介电层和设置在其上的第一电路层;布置在基板的一部分上的波导层，第二介电层，凸结构和第二电路层。 第二介电层设置在基板和波导层上。 第二电介质层具有暴露波导层的侧壁和第一电路层的一部分的开口。 凸形结构设置在波导层的侧壁上。 凸形结构和波导层分别具有折射率n1和n2，| n1-n21 | n1 <1％。 凸结构的表面粗糙度小于波导层的侧壁的表面粗糙度。 第二电路层设置在第二电介质层上。
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公开(公告)号：US20140033526A1
公开(公告)日：2014-02-06
申请号：US14052443
申请日：2013-10-11
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tsung-Yuan Chen , Ming-Huang Ting
IPC: H05K3/40
CPC classification number: H05K3/4007 , H01L21/6835 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2221/68304 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2221/68386 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/2919 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81903 , H01L2224/83005 , H01L2224/83203 , H01L2224/8385 , H01L2224/83862 , H01L2224/9211 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/14 , H05K1/186 , H05K1/187 , H05K3/4614 , H05K3/4647 , H05K2201/10674 , H05K2203/063 , Y10T29/49124 , Y10T29/49128 , H01L2224/81 , H01L2224/83 , H01L2224/19 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A fabricating method of an embedded package structure includes following steps. First and second boards are combined to form an integrated panel. First and second circuit structures are respectively formed on the first and second boards that are then separated. An embedded element is electrically disposed on the first circuit structure. First and second conductive bumps are respectively formed on a conductive circuit substrate and the second circuit structure. First and second semi-cured films are provided; a laminating process is performed to laminate the first circuit structure on the first board, the first and second semi-cured films, the conductive circuit substrate, and the second circuit structure on the second board. The first and second semi-cured films encapsulate the embedded element. The first and second conductive bumps respectively pierce through the first and second semi-cured films and are electrically connected to the first circuit structure and the conductive circuit substrate, respectively.
Abstract translation: 嵌入式封装结构的制造方法包括以下步骤。 第一和第二板组合形成集成面板。 第一和第二电路结构分别形成在第一和第二板上，然后分离。 嵌入式元件电气地布置在第一电路结构上。 第一和第二导电凸块分别形成在导电电路基板和第二电路结构上。 提供第一和第二半固化膜; 执行层压工艺以将第一板上的第一电路结构，第二和第二半固化膜，导电电路基板和第二电路结构层叠在第二板上。 第一和第二半固化膜封装了嵌入元件。 第一和第二导电凸块分别穿过第一和第二半固化膜，并分别电连接到第一电路结构和导电电路基板。
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公开(公告)号：US20130206467A1
公开(公告)日：2013-08-15
申请号：US13846875
申请日：2013-03-18
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
CPC classification number: H05K3/06 , H05K1/0298 , H05K3/465 , H05K2201/0347 , Y10T29/49126 , Y10T29/49165
Abstract: A circuit board includes a circuit substrate, a first dielectric layer, a first conductive layer, a second conductive layer and a second dielectric layer. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer, and an intaglio pattern. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via. The second conductive layer is electrically connected to the first circuit layer via the first conductive layer. The second dielectric layer is disposed on the first dielectric layer and covers the second conductive layer and the second surface of the first dielectric layer.
Abstract translation: 电路板包括电路基板，第一介电层，第一导电层，第二导电层和第二介电层。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔以及凹版图案。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中。 第二导电层经由第一导电层电连接到第一电路层。 第二电介质层设置在第一电介质层上并覆盖第二导电层和第一介电层的第二表面。
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公开(公告)号：US12218017B2
公开(公告)日：2025-02-04
申请号：US17586106
申请日：2022-01-27
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Wen Yu Lin , Kai-Ming Yang , Pu-Ju Lin
Abstract: The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.
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