摘要:
A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要:
A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top metalized contact of die two to the bottom surface of die one while accommodating for elevation difference between the surfaces. The elevation-adaptive electrical connection includes: a) An L-shaped circuit route that is part of the circuit substrate, extending transversely from a die one longitudinal edge and placing an intermediate contact area next to a die two transverse edge. b) An interconnection plate connecting the top metalized contact area of die two with the intermediate contact area while being formed to accommodate for elevation difference between the contact areas. Consequently, the semiconductor package reduces the inter-die distance from an otherwise direct transverse circuit routing between the longitudinal edges of the dies.
摘要:
A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line. In still other embodiments, methods are disclosed that include forming a non volatile memory cell include forming a first electrode; forming a variable resistive layer on the first electrode; depositing a two phase alloy layer on the variable resistive layer; converting the two phase alloy layer to a filament growth layer; and depositing a second electrode on the filament growth layer, thereby forming a non volatile memory cell.
摘要:
A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.
摘要:
Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.
摘要:
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要:
A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.
摘要:
A flip chip mounted semiconductor device package having a dimpled leadframe is disclosed. The semiconductor device package includes a leadframe having a plurality of source dimples and a gate dimple, and a semiconductor die having a plurality of source contact areas and a gate contact area corresponding to the leadframe source dimples and gate dimple respectively, the semiconductor die being flipped onto the leadframe such that cured conductive epoxy provides electrical and mechanical contact between the plurality of source contact areas and the plurality of source dimples, and the gate contact area and the gate dimple.
摘要:
An improved sliding bearing apparatus and method utilize a snap-in polymer bearing insert having one or more identically shaped locking lugs, each of which are configured for locking engagement with a corresponding depression in a bearing housing, to thereby lock the bearing insert in place against relative movement either radially or axially with respect to the bearing housing. In a free-standing state, the insert may have a variety of shapes including cylindrical, non-cylindrical, or be flat and planar. An insert for a closed bearing is configured such that it may be trimmed to form an insert for an open bearing.
摘要:
A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.