High density planar electrical interface

    公开(公告)号:US07108546B2

    公开(公告)日:2006-09-19

    申请号:US09886521

    申请日:2001-06-20

    CPC classification number: G01R1/0466 H01R13/025 H01R13/40 H01R2201/20

    Abstract: An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.

    Programmable devices to route signals on probe cards
    103.
    发明申请
    Programmable devices to route signals on probe cards 有权
    用于在探针卡上路由信号的可编程设备

    公开(公告)号:US20060170435A1

    公开(公告)日:2006-08-03

    申请号:US11048167

    申请日:2005-01-31

    CPC classification number: G01R31/31926 G01R1/07385 G01R31/2889

    Abstract: A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC now with a known delay to connect to a device being tested.

    Abstract translation: 晶片测试系统的探针卡包括一个或多个可编程IC(例如FPGA),以提供从各个测试信号通道到多个探针之一的路由。 可编程IC可以放置在探针卡的基板上,也可以放置在与探针卡相连的子卡上。 具有可编程性,PCB可用于将有限的测试系统通道切换为未使用的探头。 可编程性进一步使单个探针卡能够更有效地测试具有相同焊盘阵列但具有针对不同器件选项的不同引脚的器件。 可重编程序还允许测试工程师在调试测试程序时进行重新编程。 因为可编程IC通常包括引入未知延迟的缓冲器,在一个实施例中,通过首先对可编程IC进行编程以提供到测试系统的回送路径来实现延迟的测量,从而可以测量缓冲器延迟,然后重新编程 可编程IC现在具有已知的延迟以连接到被测试的设备。

    Probe card configuration for low mechanical flexural strength electrical routing substrates
    104.
    发明授权
    Probe card configuration for low mechanical flexural strength electrical routing substrates 失效
    用于低机械抗弯强度电路基板的探针卡配置

    公开(公告)号:US07071715B2

    公开(公告)日:2006-07-04

    申请号:US10771099

    申请日:2004-02-02

    CPC classification number: G01R31/2889 G01R1/07378

    Abstract: A mechanical support configuration for a probe card of a wafer test system is provided to increase support for a very low flexural strength substrate that supports spring probes. Increased mechanical support is provided by: (1) a frame around the periphery of the substrate having an increased sized horizontal extension over the surface of the substrate; (2) leaf springs with a bend enabling the leaf springs to extend vertically and engage the inner frame closer to the spring probes; (3) an insulating flexible membrane, or load support member machined into the inner frame, to engage the low flexural strength substrate farther away from its edge; (4) a support structure, such as support pins, added to provide support to counteract probe loading near the center of the space transformer substrate; and/or (5) a highly rigid interface tile provided between the probes and a lower flexural strength space transformer substrate.

    Abstract translation: 提供了用于晶片测试系统的探针卡的机械支撑结构,以增加对支撑弹簧探针的极低弯曲强度基底的支撑。 通过以下方式提供增加的机械支撑:(1)围绕基板的周边的框架,在基板的表面上具有增大尺寸的水平延伸; (2)具有弯曲的板簧,使得板簧能够垂直延伸并使内框架接近弹簧探针; (3)绝缘柔性膜或加工到内框架中的负载支撑构件,使低弯曲强度基板与其边缘更远地接合; (4)加载支撑结构,例如支撑销,以提供支撑以抵消在空间变压器基板的中心附近的探头负载; 和/或(5)设置在所述探针与下弯曲强度空间变换器基板之间的高刚性界面砖。

    Bi-directional buffer for interfacing test system channel
    106.
    发明申请
    Bi-directional buffer for interfacing test system channel 有权
    用于接口测试系统通道的双向缓冲器

    公开(公告)号:US20060132158A1

    公开(公告)日:2006-06-22

    申请号:US11018211

    申请日:2004-12-21

    Applicant: Charles Miller

    Inventor: Charles Miller

    CPC classification number: G01R31/2889 G01R31/31713

    Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bidirectional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

    Abstract translation: 在DUT和测试系统控制器之间的晶片测试系统的通道中提供射极跟随器或源极跟随器晶体管,以使低功率DUT能够驱动测试系统通道。 旁路电阻包括在射极跟随器晶体管的基极和发射极之间,以便在DUT通道和测试系统控制器之间提供双向信号,以及执行参数测试。 射极跟随器晶体管和旁路电阻可以在探针卡上提供,测试系统控制器中包含一个下拉终端电路。 测试系统控制器可以为射极跟随器晶体管的基极到发射极电压降提供补偿。

    Electroform spring built on mandrel transferable to other surface
    108.
    发明申请
    Electroform spring built on mandrel transferable to other surface 失效
    电铸弹簧内置在心轴上可转移到其他表面

    公开(公告)号:US20060085976A1

    公开(公告)日:2006-04-27

    申请号:US10971489

    申请日:2004-10-22

    Abstract: Resilient spring contact structures are manufactured by plating the contact structures on a reusable mandrel, as opposed to forming the contact structures on sacrificial layers that are later etched away. In one embodiment, the mandrel includes a form or mold area that is inserted through a plated through hole in a substrate. Plating is then performed to create the spring contact on the mold area of the mandrel as well as to attach the spring contact to the substrate. In a second embodiment, the mandrel includes a form that is initially plated to form the resilient contact structure and then attached to a region of a substrate without being inserted through the substrate. Attachment in the second embodiment can be achieved during the plating process used to form the spring contact, or by using a conductive adhesive or solder either before or after releasing the spring contact from the mandrel.

    Abstract translation: 通过将接触结构电镀在可重复使用的心轴上来制造弹性弹性接触结构,而不是在随后蚀刻掉的牺牲层上形成接触结构。 在一个实施例中,心轴包括通过衬底中的电镀通孔插入的形状或模具区域。 然后进行电镀以在心轴的模具区域上产生弹簧接触以及将弹簧接触件附接到基底。 在第二实施例中,心轴包括最初电镀以形成弹性接触结构然后在不插入衬底的情况下附着到衬底的区域的形式。 在用于形成弹簧接触的电镀工艺期间,或者在从芯棒释放弹簧接触之前或之后使用导电粘合剂或焊料,可以实现第二实施例中的附接。

    Methods for making plated through holes usable as interconnection wire or probe attachments

    公开(公告)号:US07024763B2

    公开(公告)日:2006-04-11

    申请号:US10723269

    申请日:2003-11-26

    Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside. In a third embodiment, a layer of masking material is initially deposited on a substrate and etched to form holes which are filled with a sacrificial fill material, the masking material is then removed, the fill material plated, grinding is performed to remove some plating to expose the fill material, and the fill material is then etched away leaving plated attachment wells. Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure is formed by supporting twisted sacrificial wires coated with the plating material in a substrate, and later etching away the wires.

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