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    Manufacturing method of semiconductor structure
    111.
    发明授权
    Manufacturing method of semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US09450015B2

    公开(公告)日：2016-09-20

    申请号：US15086809

    申请日：2016-03-31

    Applicant: XINTEC INC.

    Inventor： Wei-Ming Chien ,  Chia-Sheng Lin ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: H01L27/146 ,  H01L21/768 ,  H01L33/62

    CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
    112.
    发明申请
    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF 审中-公开
    芯片尺寸感应芯片包装及其制造方法

    公开(公告)号：US20160266680A1

    公开(公告)日：2016-09-15

    申请号：US15061858

    申请日：2016-03-04

    Applicant: XINTEC INC.

    Inventor： Shu-Ming CHANG ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC: G06F3/044 ,  H01L21/52 ,  G06F21/32 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31

    CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06K9/00006 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L2221/68327 ,  H01L2224/11

    Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

    Abstract translation: 本发明提供了一种芯片级感测芯片封装，包括具有彼此相对的第一顶表面和第一底表面的感测芯片，具有彼此相对的第二顶表面和第二底表面的触摸板， 感测芯片和夹在感测芯片和触摸板之间的彩色层，其中感测芯片包括在第一顶表面附近形成的感测装置，以及在第一顶表面附近形成并邻近感测的多个导电焊盘 多个通孔硅通孔，暴露其形成在第一底表面上的相应的导电焊盘，形成在第一底表面上的多个导电结构，以及覆盖第一底表面和每个穿过硅通孔的再分配层， 连接每个导电焊盘和每个导电结构。

    Semiconductor structure having stage difference surface and manufacturing method thereof
    114.
    发明授权
    Semiconductor structure having stage difference surface and manufacturing method thereof 有权
    具有台阶差的半导体结构及其制造方法

    公开(公告)号：US09275963B2

    公开(公告)日：2016-03-01

    申请号：US14199640

    申请日：2014-03-06

    Applicant: XINTEC INC.

    Inventor： Yung-Tai Tsai ,  Shu-Ming Chang ,  Chun-Wei Chang ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78

    CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

    Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

    Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。

    Chip package and method of manufacturing the same
    115.
    发明授权
    Chip package and method of manufacturing the same 有权
    芯片封装及其制造方法

    公开(公告)号：US09269837B2

    公开(公告)日：2016-02-23

    申请号：US14682888

    申请日：2015-04-09

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

    IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

    CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

    Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

    Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

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