公开(公告)号：US20160054521A1

公开(公告)日：2016-02-25

申请号：US14827779

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki ,  Ken Ozawa ,  Tatsuya Usami ,  Yoshiaki Yamamoto ,  Keiji Sakamoto

IPC: G02B6/125 ,  G02B6/136 ,  G02B6/293

CPC classification number: G02B6/125 ,  G02B6/136 ,  G02B2006/12061

Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.

Abstract translation: 公开了一种可以提高光偏移精度并且抑制光传输损失的光半导体装置。 在该装置中，光学耦合区域的第一光学耦合部分的内侧表面和该区域的第二光学耦合部分的内侧表面的线边缘粗糙度增加。 这种方式使光耦合容易从第一至第二光波导。 相比之下，线边缘粗糙度降低：光耦合区域的第一光耦合部分的外侧表面; 该区域的第二光耦合部分的外侧表面; 第一光波导的一部分的两个相对的侧表面，该部分是除该区域之外的任何部分; 以及第二光波导的一部分的两个相对的侧表面，该部分是该区域以外的任何部分。

公开(公告)号：US09123571B2

公开(公告)日：2015-09-01

申请号：US14137839

申请日：2013-12-20

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakashiba

IPC: G01R31/26 ,  H01L49/02 ,  G01R31/302 ,  G01R31/315 ,  H01L23/00 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L28/10 ,  G01R31/3025 ,  G01R31/315 ,  H01L22/14 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/5446 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface.

Abstract translation: 一种半导体器件，包括具有主表面和与主表面相对的后表面的第一衬底，包括形成在主表面上的多个晶体管的第一电路，形成在主表面上以覆盖第一电路的第一绝缘膜 形成在所述主表面上的所述第一绝缘膜中的第一电感器，所述第一电感器电连接到所述第一电路; 以及形成在所述主表面上的接合焊盘，所述接合焊盘位于第一区域处，所述第一电感器位于第二区域，所述第一区域在平面图中不同于所述第二区域，所述第二基板具有 主表面，与主表面相对的后表面和形成在主表面上的第二电感器。

公开(公告)号：US09054073B2

公开(公告)日：2015-06-09

申请号：US14339013

申请日：2014-07-23

Applicant: Renesas Electronics Corporation

Inventor： Akira Matsumoto ,  Yoshinao Miura ,  Yasutaka Nakashiba

IPC: H01L29/417 ,  H01L27/088 ,  H01L27/02 ,  H01L23/50

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US09013025B2

公开(公告)日：2015-04-21

申请号：US14148893

申请日：2014-01-07

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba

IPC: H01L27/08 ,  H01F21/12 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01F21/12 ,  H01F21/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings.

Abstract translation: 电感器件包括绝缘层，电感器，固定电极和可动电极。 电感器形成在绝缘层上。 固定电极设置在平面图中不与电感器重叠的位置。 可动电极在平面图中与电感器和固定电极重叠，并且与电感器和固定电极分离。 此外，可动电极包括第一开口。

公开(公告)号：US20150061645A1

公开(公告)日：2015-03-05

申请号：US14477538

申请日：2014-09-04

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida

IPC: G01R1/20 ,  G01R19/00

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R15/181

Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.

Abstract translation: 本发明以更低的成本提供传感器装置。 传感器装置包括印刷电路板，第一端子，第二端子，互连线和半导体器件。 第一端子和第二端子设置在印刷电路板上并耦合到电力线。 第二端子相对于第一端子耦合到电力线的下游部分。 互连线布置在印刷电路板上以将第一端子和第二端子彼此耦合。 换句话说，互连线并联耦合到电力线。 半导体器件安装在印刷电路板上，并且包括形成在互连层中的互连层和电感器。

公开(公告)号：US08896095B2

公开(公告)日：2014-11-25

申请号：US14176193

申请日：2014-02-10

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L23/522 ,  H01L23/48 ,  H01L25/065 ,  H01F17/00 ,  H01F38/14

CPC classification number: H01L25/0655 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/528 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract translation: 在半导体器件中，第一半导体芯片包括第一电路和第一电感器，第二半导体芯片包括第二电路和芯片侧连接端子。 互连基板被放置在第一半导体芯片和第二半导体芯片上。 互连基板包括第二电感器和基板侧连接端子。 第二电感器位于第一电感器的上方。 芯片侧连接端子和两个基板侧连接端子通过第一焊球连接。

公开(公告)号：US08780237B2

公开(公告)日：2014-07-15

申请号：US13677877

申请日：2012-11-15

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H04N7/18 ,  H04N7/00 ,  H04N5/222 ,  H04N9/083 ,  H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  G09B9/00

CPC classification number: H04N5/33 ,  G06K9/0004 ,  H04N9/045

Abstract: A solid-state imaging apparatus 10 includes a solid-state imaging device 40, and a color filter 16 constituted of a first color filter 16a (first filter) and a second color filter 16b (second filter). The solid-state imaging device 40 photoelectrically converts light incident to a face S1 (first face) thereof to thereby capture an image of an object to be imaged. Arranged on the face S1 of the solid-state imaging device 40 is the first color filter 16a and second color filter 16b. The first color filter 16a is a filter that allows first wavelength band light to be selectively transmitted therethrough; the second color filter 16b is a filter that allows second wavelength band light in the longer wavelength side relative to the first wavelength band to be selectively transmitted therethrough.

Abstract translation: 固态成像装置10包括固态成像装置40和由第一滤色器16a（第一滤色器）和第二滤色器16b（第二滤色器）构成的滤色器16。 固态成像装置40对入射到其表面S1（第一面）的光进行光电转换，从而捕获待成像对象的图像。 在固态成像装置40的面S1上排列的是第一滤色器16a和第二滤色器16b。 第一滤色器16a是允许选择性地透过第一波长带光的滤光器; 第二滤色器16b是允许通过其选择性地透射相对于第一波长带的较长波长侧的第二波长带光的滤光器。

公开(公告)号：US20140191363A1

公开(公告)日：2014-07-10

申请号：US14203037

申请日：2014-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Kenta Ogawa

IPC: H01L49/02

CPC classification number: H01L28/10 ,  G11C5/005 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0949 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/1316 ,  H05K2203/1572 ,  Y10T29/4902 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.

Abstract translation: 一种外部存储装置，包括具有接触型外部端子的互连基板，设置在所述互连基板的第一表面上的至少一个半导体芯片以及密封所述至少一个半导体芯片并且不覆盖所述外部端子的密封树脂层 。 所述至少一个半导体芯片包括存储装置，连接到所述存储装置的电感器，被配置为控制所述电感器和互连层的驱动器电路。 互连层形成在半导体芯片的第一表面并且包括电感器。 半导体芯片的第一表面不是面向互连衬底的第一表面，并且电感器和驱动电路通过互连层相互连接。

公开(公告)号：US08729651B2

公开(公告)日：2014-05-20

申请号：US13711178

申请日：2012-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L49/02

CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303 ,  H01L23/48 ,  H01L23/645 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate, a bonding pad provided above the substrate, a first signal transmitting/receiving portion provided above the substrate and below the bonding pad, and a transistor provided over the substrate. The transistor is connected to the first signal transmitting/receiving portion provided in a layer of the semiconductor device.

Abstract translation: 半导体器件包括衬底，设置在衬底上的接合焊盘，设置在衬底上方并在焊盘下方的第一信号发射/接收部分和设置在衬底上的晶体管。 晶体管连接到设置在半导体器件的层中的第一信号发送/接收部分。

公开(公告)号：US20130062731A1

公开(公告)日：2013-03-14

申请号：US13671428

申请日：2012-11-07

Applicant: Renesas Electronics Corporation

Inventor： Masayuki Furumiya ,  Yasutaka Nakashiba

IPC: H01L27/06

CPC classification number: H01L28/10 ,  G01R31/3025 ,  G01R31/315 ,  H01L22/14 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/5446 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

Abstract translation: 半导体器件包括具有主表面和后表面的衬底，在主表面侧形成的晶体管，在主表面侧形成的绝缘体层，形成在绝缘体层上的电感器和 主表面，与电感器重叠并形成在主表面的一侧的带;以及形成在绝缘层和主表面一侧上的接合焊盘。 在没有接合焊盘的区域上选择性地形成带。