公开(公告)号：US11387143B2

公开(公告)日：2022-07-12

申请号：US17085619

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20220102269A1

公开(公告)日：2022-03-31

申请号：US17213650

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Li Yang ,  Po-Hao Tsai ,  Ming-Da Cheng ,  Yung-Han Chuang ,  Hsueh-Sheng Wang

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/528 ,  H01L23/00

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

公开(公告)号：US11251141B2

公开(公告)日：2022-02-15

申请号：US16888758

申请日：2020-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Yu-Chih Huang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Chih-Hua Chen ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20210066226A1

公开(公告)日：2021-03-04

申请号：US16866562

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chiang-Jui Chu ,  Ching-Wen Hsiao ,  Hao-Chun Liu ,  Ming-Da Cheng ,  Young-Hwa Wu ,  Tao-Sheng Chang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.

公开(公告)号：US10672729B2

公开(公告)日：2020-06-02

申请号：US15726260

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Yu-Chih Huang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Chih-Hua Chen ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

公开(公告)号：US10177104B2

公开(公告)日：2019-01-08

申请号：US15631436

申请日：2017-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/03 ,  H01L25/00 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

公开(公告)号：US10050001B2

公开(公告)日：2018-08-14

申请号：US15268693

申请日：2016-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Bor-Rung Su

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L21/28 ,  H01L21/302 ,  H01L23/00 ,  H01L23/482 ,  H01L21/56 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.

公开(公告)号：US09947552B2

公开(公告)日：2018-04-17

申请号：US15195321

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Meng-Tse Chen ,  Hui-Min Huang ,  Ming-Da Cheng ,  Kuo-Lung Pan ,  Wei-Sen Chang ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

公开(公告)号：US09711470B2

公开(公告)日：2017-07-18

申请号：US14975911

申请日：2015-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  B23K35/02 ,  B23K35/36 ,  B23K35/26 ,  B23K35/22 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L25/03 ,  H01L25/00 ,  B23K35/00

CPC classification number: H01L24/05 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3613 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/06181 ,  H01L2224/08113 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1355 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13666 ,  H01L2224/1412 ,  H01L2224/14181 ,  H01L2224/16104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

公开(公告)号：US09691745B2

公开(公告)日：2017-06-27

申请号：US13927568

申请日：2013-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： James Hu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L29/24 ,  H01L21/76 ,  H01L25/04 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/11 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0001

Abstract: Embodiments of mechanisms of a semiconductor device package and package on package (PoP) structure are provided. The semiconductor device package includes a substrate and a metal pad formed on the substrate. The semiconductor device package further includes a conductive element formed on the metal pad, and the metal pad electrically contacts the conductive element, and at least a portion of the conductive element is embedded in a molding compound, and the conductive element has a recess configured to provide an additional bonding interfacial area.