公开(公告)号：US20020182778A1

公开(公告)日：2002-12-05

申请号：US09865417

申请日：2001-05-29

发明人： Pei-Wei Wang ,  Chin-Jung Chang

IPC分类号： H01L021/50

CPC分类号： H01L21/6835 ,  H01L23/5387 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flexible package fabrication method, which enables the IC chip packaging film and the inner lead automated bonding to be simultaneously done. The method includes the steps of preparing a base member, electroplating a circuit having inner leads, outer leads, test lines/test terminals on the base member, covering the top side of the circuit with a polyimide passivation film or layer of flexible solder protective paint, bonding the bumps of a bumped IC chip or passive element to the inner leads of the circuit by thermocompression bonding, removing the base member, and covering the bottom side of the circuit with a polyimide passivation layer or layer of flexible solder protective paint.

摘要翻译： 一种灵活的封装制造方法，能够同时进行IC芯片封装膜和内部引线自动接合。 该方法包括以下步骤：准备基底部件，在基底部件上电镀具有内部引线，外部引线，测试线/测试端子的电路，用聚酰亚胺钝化膜或柔性焊料保护涂层覆盖电路的顶侧 通过热压接将凸起的IC芯片或无源元件的凸起接合到电路的内引线，去除基底构件，并用聚酰亚胺钝化层或柔性焊料保护涂层覆盖电路的底侧。

公开(公告)号：US20020130391A1

公开(公告)日：2002-09-19

申请号：US10147029

申请日：2002-05-15

发明人： Nai Hua Yeh ,  Chen Pin Peng ,  Jichen Wu

IPC分类号： H01L029/12

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connecting to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits. According to the structure, the problem caused by the overflowed glue in the integrated circuit can be effectively avoided. A method for manufacturing the structure is also disclosed.

摘要翻译： 集成电路的封装结构包括衬底，集成电路，粘合剂层，多个布线和胶层。 基板具有第一表面和第二表面。 第一表面形成有多个信号输入端子。 第二表面形成有用于电连接到电路板的多个信号输出端子。 集成电路具有下表面和上表面。 凹部形成在下表面的两侧，并且在上表面上形成多个接合焊盘。 粘合剂层用于将集成电路的下表面粘附到基板的第一表面。 布线电连接到集成电路的接合焊盘和衬底的信号输入端。 胶层用于密封多根配线和集成电路。 根据该结构，可以有效地避免集成电路中溢出的胶水引起的问题。 还公开了一种制造该结构的方法。

公开(公告)号：US06437427B1

公开(公告)日：2002-08-20

申请号：US09391792

申请日：1999-09-08

申请人： Yeon Ho Choi

发明人： Yeon Ho Choi

IPC分类号： H01L23495

CPC分类号： H01L23/49503 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A lead frame for a semiconductor package including a rectangular lead frame body having a central opening, a plurality of leads arranged at and along each of two or four facing sides of the lead frame body, the leads extending in flush with the lead frame body, and a semiconductor chip mounting plate positioned on a plane not flush with a plane, where the leads are positioned, the semiconductor chip mounting plate being supported by down-set tie bars and provided with at least one groove having a rectangular ring shape while serving to prevent a penetration of moisture and to provide an increased coupling strength for the semiconductor chip mounting plate, the semiconductor chip mounting plate also serving as a heat sink. A ground bridge bar having a rectangular ring shape is arranged between the semiconductor chip mounting plate and the leads and supported by another tie bars. By virtue of the bridge bar, the length of bonding wires is reduced, thereby eliminating the possibility of the bonding wires to be short-circuited. A lead frame having a double down-set structure is also provided. By virtue of the double down-set structure, it is possible to increase the size of the semiconductor chip mounting plate, thereby achieving an improvement in the heat discharge effect.

摘要翻译： 一种用于半导体封装的引线框架，包括具有中心开口的矩形引线框架体，沿着引线框架主体的两个或四个相对侧中的每一个布置的多个引线，引线与引线框架主体齐平地延伸， 以及半导体芯片安装板，其位于不与引线定位的平面不平齐的平面上，半导体芯片安装板由下降的连接杆支撑并设置有至少一个具有矩形环形的凹槽，同时用于 防止水分渗透，并为半导体芯片安装板提供增加的耦合强度，半导体芯片安装板也用作散热片。 在半导体芯片安装板和引线之间布置具有矩形环形的接地桥杆，并由另一个连接杆支撑。 借助于桥接条，键合线的长度减小，从而消除了接合线短路的可能性。 还提供了具有双重下降结构的引线框架。 通过双重下降结构，可以增加半导体芯片安装板的尺寸，从而实现放热效果的提高。

公开(公告)号：US20020096766A1

公开(公告)日：2002-07-25

申请号：US09770054

申请日：2001-01-24

发明人： Wen Chuan Chen ,  Kuo Feng Peng ,  C. H. Chou ,  Allis Chen ,  Nai Hua Yeh ,  Yen Cheng Huang ,  C. F. Wang ,  Chen Pin Peng ,  Wen Tsan Lee ,  Jichen Wu

IPC分类号： H01L023/48 ,  H01L029/40 ,  H01L023/544 ,  H01L023/52 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connecting to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits. According to the structure, the problem caused by the overflowed glue in the integrated circuit can be effectively avoided. A method for manufacturing the structure is also disclosed.

摘要翻译： 集成电路的封装结构包括衬底，集成电路，粘合剂层，多个布线和胶层。 基板具有第一表面和第二表面。 第一表面形成有多个信号输入端子。 第二表面形成有用于电连接到电路板的多个信号输出端子。 集成电路具有下表面和上表面。 凹部形成在下表面的两侧，并且在上表面上形成多个接合焊盘。 粘合剂层用于将集成电路的下表面粘附到基板的第一表面。 布线电连接到集成电路的接合焊盘和衬底的信号输入端。 胶层用于密封多根配线和集成电路。 根据该结构，可以有效地避免集成电路中溢出的胶水引起的问题。 还公开了一种制造该结构的方法。

公开(公告)号：US20020084518A1

公开(公告)日：2002-07-04

申请号：US09988644

申请日：2001-11-20

发明人： Hajime Hasebe ,  Tadatoshi Danno ,  Yukihiro Satou

IPC分类号： H01L023/495

CPC分类号： H01L23/49503 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A non-leaded type semiconductor device comprising a tab, tab suspension leads, plural leads, the tab, the tab suspension leads and the plural leads being exposed to one surface of the seal member, a semiconductor element positioned within the seal member and fixed to a surface of the tab with an adhesive, electrically conductive wires for electrically connecting electrodes on the semiconductor element and the leads with each other, and electrically conductive wires for electrically connecting the electrodes on the semiconductor element and a tab surface portion deviated from the semiconductor element with each other, wherein the tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element, a groove is formed in the tab surface portion positioned between a semiconductor element fixing area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, the tab has a section which is in the shape of an inverted trapezoid, and peripheral edges of the tab bite into a package. Not only the reliability of wire connection, including down bonding, is improved, but also it is possible to prevent peeling-off between the tab to which the semiconductor element is fixed and resin which constitutes the package.

摘要翻译： 一种非铅型半导体器件，包括：突片，突片悬挂引线，多个引线，突片，突片悬挂引线和暴露于密封构件的一个表面的多个引线;半导体元件，定位在密封构件内并固定到 具有粘合剂的突片的表面，用于将半导体元件上的电极和引线彼此电连接的导电线和用于电连接半导体元件上的电极的导电线和偏离半导体元件的突片表面部分 彼此相对，其中突片形成为大于半导体元件，使得突片的外周边缘位于半导体元件的外周边缘外侧，在位于半导体元件固定区域到半导体元件固定区域 半导体元件固定，导线所在的导线连接区域 所述槽形成为围绕半导体元件固定区域，所述突片具有呈倒梯形的部分，并且所述突片的外围边缘咬入到封装中。 不仅提高了包括下焊的电线连接的可靠性，而且可以防止半导体元件固定的突片与构成封装的树脂之间的剥离。

公开(公告)号：US06414397B1

公开(公告)日：2002-07-02

申请号：US09601041

申请日：2000-07-26

申请人： Toshihiro Sawamoto

发明人： Toshihiro Sawamoto

IPC分类号： H01L2329

CPC分类号： H05K3/323 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15787 ,  H05K2201/0187 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00

摘要： An anisotropic conductive film includes hard portions at the two edges and a soft portion constituting the remainder. Due to such a construction, when a semiconductor chip is bonded to a substrate by thermocompression, the hard portions inhibit the soft portion from flowing toward the periphery of the semiconductor chip. Thereby, it is possible to prevent the anisotropic conductive film from adhering to a hot pressing tool.

摘要翻译： 各向异性导电膜包括在两个边缘处的硬部分和构成其余部分的软部分。 由于这样的结构，当半导体芯片通过热压接合到基板时，硬部分阻止软部分朝向半导体芯片的周边流动。 由此，可以防止各向异性导电膜附着在热压工具上。

公开(公告)号：US20020071253A1

公开(公告)日：2002-06-13

申请号：US10066023

申请日：2002-01-30

发明人： Allen K. Lam ,  Richard K. Williams ,  Alex K. Choi

IPC分类号： H05K007/20

CPC分类号： H01L24/97 ,  H01L23/4334 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die. To avoid shorting between adjacent leads, moats are formed in the leads where they face the die to prevent liquid epoxy or solder from spreading between the leads. Since no central tie bar is required, multiple dice can readily be packaged in a single plastic capsule.

公开(公告)号：US06368895B1

公开(公告)日：2002-04-09

申请号：US09686620

申请日：2000-10-12

申请人： Yoshitsugu Hori

发明人： Yoshitsugu Hori

IPC分类号： H01L31107

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic circuit device is provided which can avoid unnecessary spreading of a sealing resin and on which components can be mounted at a high mounting density. An enclosure for preventing the resin from flowing outside its intended boundaries and having a larger size than a chip in a chip mounting area of a circuit board is formed. The chip is mounted in a face-down orientation in the chip mounting area enclosed by the enclosure. A sealing resin is cast through a gate for casting a resin and introduced into the gap between the chip and the circuit board. It can be judged whether the charging of the resin has been completed or not, by checking the flowing of the resin into the groove.

摘要翻译： 提供一种电子电路装置，其可以避免密封树脂的不必要的扩散，并且可以以高的安装密度安装在哪些部件上。 形成用于防止树脂流过预期边界并且具有比电路板的芯片安装区域中的芯片更大的尺寸的外壳。 芯片以面朝下的方向安装在由外壳包围的芯片安装区域中。 密封树脂通过用于铸造树脂的浇口浇注并引入到芯片和电路板之间的间隙中。 可以通过检查树脂流入沟槽来判断树脂的充电是否已经完成。

公开(公告)号：US06340607B1

公开(公告)日：2002-01-22

申请号：US09631282

申请日：2000-08-03

申请人： Yukio Yamada

发明人： Yukio Yamada

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/29 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/27013 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29019 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/75 ,  H01L2224/75313 ,  H01L2224/75743 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T156/1744 ,  H01L2924/00 ,  H01L2924/00012

摘要： A process for mounting a semiconductor device and a mounting apparatus whereby electrodes of a fine-pitch semiconductor device and a wiring board can be surely connected to each other. A process for mounting a semiconductor device by electrically connecting an electrode of the semiconductor device 4 to an electrode of a wiring board by using an anisotropic conductive adhesive film having conductive particles dispersed in an insulating adhesive, which process comprising: the step of tentatively thermocompression bonding a conductive particle-free filmy insulating adhesive onto a wiring board 22 to thereby form an insulating adhesive layer 23; the step of forming a concave 23a of a predetermined size in said insulating adhesive layer 23 by using a compression bonding head 2 provided with a pressing chip 21 at a predetermined position; the step of putting in the concave 23a of said insulating adhesive layer 23 an anisotropic conductive adhesive film of a predetermined size; and the step of mounting a predetermined IC chip 11 at a predetermined position of the compression bonding head 2 and then positioning said IC chip 11 and thermocompression bonding to said wiring board 22.

摘要翻译： 一种用于安装半导体器件和安装设备的方法，其中精细间距半导体器件和布线板的电极可以彼此可靠地连接。1.一种通过将半导体器件4的电极电连接到 通过使用具有分散在绝缘粘合剂中的导电性粒子的各向异性导电性粘接膜的布线基板的电极，该方法包括：将无导电性粒子的膜绝缘性粘接剂暂时热压接合到配线基板22上，由此形成绝缘体 粘合剂层23; 通过使用在预定位置设置有加压芯片21的压接头2，在所述绝缘粘合剂层23中形成预定尺寸的凹部23a的步骤; 将绝缘粘合剂层23的凹部23a放入预定尺寸的各向异性导电粘合膜的步骤; 以及将预定的IC芯片11安装在压接头2的预定位置，然后将所述IC芯片11定位并热压接到所述布线板22上的步骤。

公开(公告)号：US06331451B1

公开(公告)日：2001-12-18

申请号：US09434546

申请日：1999-11-05

申请人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

发明人： James M. Fusaro ,  Robert F. Darveaux ,  Pablo Rodriguez

IPC分类号： H01L2158

CPC分类号： H01L24/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49128 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods of making integrated circuit device packages and substrates for making the packages are disclosed. An embodiment of a method of making a substrate includes providing an unpatterned sheet of polyimide material having a first surface and an opposite second surface. A planar metal layer is attached to the second surface of the polyimide sheet. The metal layer is patterned to form an array of package sites, with each site including a planar die pad and planar leads. Apertures are formed through the polyimide sheet, either before or after attaching the metal layer. Each aperture is juxtaposed with a lead allowing access thereto. A method of making a package using the substrate includes mounting an integrated circuit device above the die pad (e.g., on the substrate or on the die pad through an aperture in the substrate). Bond wires are connected between the integrated circuit device and the leads through the apertures. An insulative encapsulant is applied so as to cover the integrated circuit device and fill the apertures. A method of making multiple packages includes a final step of cutting an encapsulated array of package sites with a saw to separate individual packages.

摘要翻译： 公开了制造集成电路器件封装和制造封装的衬底的方法。 制造基板的方法的实施例包括提供具有第一表面和相对的第二表面的未图案化的聚酰亚胺材料片。 平面金属层附接到聚酰亚胺片的第二表面。 将金属层图案化以形成封装位置的阵列，其中每个位置包括平面管芯焊盘和平面引线。 在安装金属层之前或之后，通过聚酰亚胺片形成孔。 每个孔与一个允许进入其的引线并置。 使用衬底制造封装的方法包括将集成电路器件安装在管芯焊盘之上（例如，在衬底上或通过衬底中的孔的芯片焊盘上）。 接合线通过孔连接在集成电路器件和引线之间。 施加绝缘密封剂以覆盖集成电路器件并填充孔。 制造多个包装的方法包括用锯切割封装位置的封装阵列以分离单独包装的最后步骤。