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    FABRIC-BASED PIEZOELECTRIC ENERGY HARVESTING
    121.
    发明申请
    FABRIC-BASED PIEZOELECTRIC ENERGY HARVESTING 审中-公开

    公开(公告)号：US20170163178A1

    公开(公告)日：2017-06-08

    申请号：US14961116

    申请日：2015-12-07

    Applicant: Intel Corporation

    Inventor： Nadine L. Dabby ,  Feras Eid ,  Adel A. Elsherbini ,  Braxton Lathrop ,  Aleksandar Aleksov ,  Sasha Oster

    IPC: H02N2/18 ,  F03G5/08

    CPC classification number: F03G5/08 ,  H01L41/113 ,  H02N2/18

    Abstract: A device for harvesting energy from fabric or clothing includes a piece of fabric or clothing. One or more piezoelectric harvesters are coupled with the piece of fabric or clothing. The piezoelectric harvesters are capable of producing electric energy in response to the movement of the piece of fabric or clothing. Additionally, the device includes one or more energy storage mediums coupled to the one or more piezoelectric harvesters. The energy storage mediums are capable of storing the energy produced by the one or more piezoelectric harvesters. Further, the method for harvesting energy from fabric or clothing involves moving a piece of fabric such that one or more piezoelectric harvesters generate electricity. The method for harvesting energy from fabric or clothing also involves storing the generated electricity in one or more energy storage mediums.

    Methods of forming sensor integrated packages and structures formed thereby
    122.
    发明授权
    Methods of forming sensor integrated packages and structures formed thereby 有权
    形成传感器集成封装和由此形成的结构的方法

    公开(公告)号：US09505607B2

    公开(公告)日：2016-11-29

    申请号：US14671549

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B7/0077 ,  B81C2203/0109

    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

    Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

    OPTICAL INTERCONNECT ON BUMPLESS BUILD-UP LAYER PACKAGE
    124.
    发明申请
    OPTICAL INTERCONNECT ON BUMPLESS BUILD-UP LAYER PACKAGE 审中-公开
    无障碍建筑层包装的光学互连

    公开(公告)号：US20160254641A1

    公开(公告)日：2016-09-01

    申请号：US15056794

    申请日：2016-02-29

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

    IPC: H01S5/022 ,  H01S5/183

    CPC classification number: H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

    Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

    Abstract translation: 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。

    Hermetic encapsulation for microelectromechanical systems (MEMS) devices
    126.
    发明授权
    Hermetic encapsulation for microelectromechanical systems (MEMS) devices 有权
    微机电系统（MEMS）器件的气密封装

    公开(公告)号：US09242854B2

    公开(公告)日：2016-01-26

    申请号：US14137538

    申请日：2013-12-20

    Applicant: Intel Corporation

    Inventor： Sarah K. Haney ,  Weng Hong Teh ,  Feras Eid ,  Sasha N. Oster

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81B7/0041 ,  B81B7/0032 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00293 ,  B81C1/00539 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/0136 ,  B81C2203/0792

    Abstract: Embodiments of the invention describe hermetic encapsulation for MEMS devices, and processes to create the hermetic encapsulation structure. Embodiments comprise a MEMS substrate stack that further includes a magnet, a first laminate organic dielectric film, a first hermetic coating disposed over the magnet, a second laminate organic dielectric film disposed on the hermetic coating, a MEMS device layer disposed over the magnet, and a plurality of metal interconnects surrounding the MEMS device layer. A hermetic plate is subsequently bonded to the MEMS substrate stack and disposed over the formed MEMS device layer to at least partially form a hermetically encapsulated cavity surrounding the MEMS device layer. In various embodiments, the hermetically encapsulated cavity is further formed from the first hermetic coating, and at least one of the set of metal interconnects, or a second hermetic coating deposited onto the set of metal interconnects.

    Abstract translation: 本发明的实施例描述了用于MEMS器件的气密封装和用于创建气密封装结构的工艺。 实施例包括进一步包括磁体的MEMS基板堆叠，第一层压有机介电膜，设置在磁体上的第一密封涂层，设置在密封涂层上的第二层压有机绝缘膜，设置在磁体上的MEMS器件层，以及 围绕MEMS器件层的多个金属互连。 密封板随后结合到MEMS衬底叠层并且设置在所形成的MEMS器件层上，以至少部分地形成围绕MEMS器件层的气密封装的腔体。 在各种实施例中，气密封装的空腔进一步由第一密封涂层形成，并且该组金属互连中的至少一个或沉积在该组金属互连件上的第二密封涂层。

    IN-PACKAGE TEMPERATURE SENSOR AND METHODS THEREFOR
    127.
    发明申请
    IN-PACKAGE TEMPERATURE SENSOR AND METHODS THEREFOR 审中-公开
    内包温度传感器及其方法

    公开(公告)号：US20150355035A1

    公开(公告)日：2015-12-10

    申请号：US14296782

    申请日：2014-06-05

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Sasha Oster ,  Sarah Haney ,  Kyu Oh Lee

    IPC: G01K11/26

    CPC classification number: G01K7/32 ,  Y10T29/4913

    Abstract: This disclosure relates generally to an electronic assembly and methods that include a dielectric material forming a cavity, a magnet positioned to induce a magnetic field within the cavity, a conductive trace positioned, at least in part, within the cavity, and a frequency detection circuit configured to detect the frequency of the maximal electromotive force as induced and produce an output proportional to a temperature of the conductive trace. The conductive trace resonates within the cavity based on a temperature-dependent resonant frequency of the conductive trace and a sinusoidal current induced through the conductive trace by a current source, the sinusoidal current induces a maximal electromotive force when a frequency of the sinusoidal current has an approximately equal magnitude to the temperature-dependent resonant frequency of the conductive trace, and the maximal electromotive force, as induced, has a substantially equal frequency as the temperature-dependent resonant frequency of the conductive trace.

    Abstract translation: 本公开总体上涉及电子组件和方法，其包括形成空腔的介电材料，定位成在空腔内引起磁场的磁体，至少部分地位于空腔内的导电迹线，以及频率检测电路 被配置为检测最大电动势的频率，并且产生与导电迹线的温度成比例的输出。 导电迹线基于导电迹线的依赖于​​温度的谐振频率和通过电流源通过导电迹线感应的正弦电流在谐振腔内谐振，当正弦电流的频率具有正弦电流时，正弦电流感应出最大电动势 与导电迹线的温度相关的谐振频率大致相等，并且如感应的最大电动势具有与导电迹线的温度相关的谐振频率基本上相等的频率。

    Liquid cooled interposer for integrated circuit stack
    128.
    发明授权
    Liquid cooled interposer for integrated circuit stack 有权

    公开(公告)号：US12300579B2

    公开(公告)日：2025-05-13

    申请号：US17346895

    申请日：2021-06-14

    Applicant: Intel Corporation

    Inventor： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

    IPC: H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H05K7/20 ,  H01L23/00

    Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

    FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES
    129.
    发明申请
    FINE-GRAIN INTEGRATION OF GROUP III-V DEVICES 有权

    公开(公告)号：US20250112210A1

    公开(公告)日：2025-04-03

    申请号：US18478932

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Han Wui Then ,  Adel Elsherbini ,  Feras Eid ,  Thomas L. Sounart ,  Georgios C. Dogiamis ,  Tushar Kanti Talukdar

    IPC: H01L25/065 ,  H01L21/683 ,  H01L21/8238 ,  H01L23/00

    Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

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