公开(公告)号：US11802042B2

公开(公告)日：2023-10-31

申请号：US17117469

申请日：2020-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Terzi

IPC: G02B26/08 ,  B81B7/00 ,  G02B7/182

CPC classification number: B81B7/008 ,  G02B7/182 ,  B81B2201/042 ,  G02B26/08

Abstract: A method of operating a MEMS device includes generating a MEMS drive signal, and generating and modifying the MEMS drive signal based upon a control signal to produce a modified drive signal. The method further includes generating the control signal by determining when a feedback signal from the MEMS device is at its peak value, comparing the peak value to a desired value when the feedback signal is as its peak, and generating the control signal depending upon whether the peak value is at least equal to a desired value. The modification of the MEMS drive signal based upon the control signal to produce the modified drive signal includes skipping generation of a next pulse of the modified drive signal when the control signal indicates the peak value is at least equal to the desired value.

公开(公告)号：US11798630B2

公开(公告)日：2023-10-24

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Fabio Enrico Carlo Disegni ,  Chantal Auricchio ,  Cesare Torti ,  Davide Manfre' ,  Laura Capecchi ,  Emanuela Calvetti ,  Stefano Zanchi

IPC: G11C16/28 ,  G11C16/10 ,  G11C7/04 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/04 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US11793406B2

公开(公告)日：2023-10-24

申请号：US17948890

申请日：2022-09-20

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Rundo ,  Francesca Trenta ,  Sabrina Conoci ,  Sebastiano Battiato

IPC: G01C22/00 ,  A61B5/00 ,  B60W60/00 ,  A61B5/024 ,  A61B5/0255 ,  A61B5/18 ,  B60W40/08 ,  B60W50/14 ,  G06N3/08 ,  G06V20/59 ,  G06V40/16 ,  G06N3/044 ,  G06F18/21 ,  G06N3/045 ,  G06V40/10

CPC classification number: A61B5/0077 ,  A61B5/0255 ,  A61B5/02405 ,  A61B5/02416 ,  A61B5/18 ,  A61B5/6893 ,  A61B5/6898 ,  A61B5/7267 ,  A61B5/7278 ,  A61B5/746 ,  B60W40/08 ,  B60W50/14 ,  B60W60/0051 ,  G06N3/044 ,  G06N3/08 ,  G06V20/597 ,  G06V40/165 ,  G06V40/166 ,  G06V40/167 ,  G06V40/171 ,  A61B2576/02 ,  B60W2050/143 ,  G06F18/217 ,  G06N3/045 ,  G06V40/15

Abstract: A method includes receiving a video signal that comprises a time series of images of a face of a human, wherein the images in the time series of images comprise a set of landmark points in the face, applying tracking processing to the video signal to reveal variations over time of at least one image parameter at the set of landmark points in the human face, generating a set of variation signals indicative of variations revealed at respective landmark points in the set of landmark points, applying processing to the set of variation signals, the processing comprising artificial neural network processing to produce a reconstructed PhotoPletysmoGraphy (PPG) signal, and estimating a heart rate variability of a variable heart rate of the human as a function of the reconstructed PPG signal.

公开(公告)号：US20230336176A1

公开(公告)日：2023-10-19

申请号：US18296325

申请日：2023-04-05

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino CONTE ,  Marco RUTA ,  Michelangelo PISASALE ,  Thomas JOUANNEAU

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018521 ,  H03K19/20

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

公开(公告)号：US20230328979A1

公开(公告)日：2023-10-12

申请号：US18185575

申请日：2023-03-17

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bregoli ,  Alessandro Ferretti ,  Federica Rosa

IPC: H10B41/70 ,  G11C16/04 ,  G11C16/10 ,  H10B41/35 ,  G11C16/14

CPC classification number: H10B41/70 ,  G11C16/045 ,  G11C16/10 ,  G11C16/14 ,  H10B41/35

Abstract: A non-volatile memory cell includes a first well of a first conductivity type and a second well of a second conductivity type in a body adjacent to each other; a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type; a control gate region, of the first or second conductivity type, in the second well; a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and a floating gate region. The floating gate region has a programming portion overlying the first well and a capacitive portion overlying the second well. The floating gate region forms, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element.

公开(公告)号：US20230326524A1

公开(公告)日：2023-10-12

申请号：US17718908

申请日：2022-04-12

Applicant: STMicroelectronics S.r.l. ,  Alma Mater Studiorum - Universita' Di Bologna

Inventor： Marco PASOTTI ,  Marcella CARISSIMI ,  Alessio ANTOLINI ,  Eleonora FRANCHI SCARSELLI ,  Antonio GNUDI ,  Andrea LICO ,  Paolo ROMELE

IPC: G11C13/00

CPC classification number: G11C13/0061 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038

Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.

公开(公告)号：US20230324674A1

公开(公告)日：2023-10-12

申请号：US18131085

申请日：2023-04-05

Applicant: STMicroelectronics S.r.l.

Inventor： Nicolo' BONI ,  Roberto CARMINATI ,  Massimiliano MERLI ,  Carlo Luigi PRELINI ,  Tarek AFIFI AFIFI

IPC: G02B26/08 ,  B81B3/00 ,  B81C1/00

CPC classification number: G02B26/0858 ,  B81B3/007 ,  B81C1/00658 ,  B81B2201/042

Abstract: A microelectromechanical mirror device has, in a die of semiconductor material: a fixed structure defining a cavity; a tiltable structure carrying a reflecting region, elastically suspended above the cavity and having a main extension in a horizontal plane; at least one first pair of driving arms, carrying respective piezoelectric structures which can be biased to generate a driving force that causes rotation of the tiltable structure about a rotation axis parallel to a first horizontal axis of the horizontal plane; elastic suspension elements, which elastically couple the tiltable structure to the fixed structure at the rotation axis and are rigid to movements out of the horizontal plane and compliant to torsion about the rotation axis. In particular, the driving arms of the first pair are magnetically coupled to the tiltable structure to cause its rotation about the rotation axis by magnetic interaction, following biasing of the respective piezoelectric structures.

公开(公告)号：US20230324475A1

公开(公告)日：2023-10-12

申请号：US18335511

申请日：2023-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Argento ,  Orazio Pennisi ,  Stefano Castorina ,  Vanni Poletto ,  Matteo Landini ,  Andrea Maino

IPC: G01R31/64 ,  G01R27/26 ,  G01R31/00

CPC classification number: G01R31/64 ,  G01R27/2605 ,  G01R31/006

Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.

公开(公告)号：US20230324229A1

公开(公告)日：2023-10-12

申请号：US18335003

申请日：2023-06-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Maria Eloisa CASTAGNA ,  Giuseppe BRUNO

IPC: G01J5/16 ,  G01J5/20 ,  H01L27/146 ,  H04N5/33

CPC classification number: G01J5/16 ,  G01J5/20 ,  H01L27/14669 ,  H04N5/33 ,  G01J2005/0077

Abstract: A thermographic sensor is proposed. The thermographic sensor includes a plurality of sensing elements each comprising at least one thermo-couple. The thermographic sensor is integrated on a semiconductor on insulator body that is patterned to define a grid suspended from a substrate; for each sensing element, the grid has a frame with the cold joint of the thermo-couple, a plate with the hot joint of the thermo-couple and one or more arms sustaining the plate from the frame. The frames include one or more conductive layers of thermally conductive material for thermally equalizing the cold joints with the substrate. Moreover, each sensing element may also include a processing circuit for the thermo-couple that is integrated on the corresponding frame. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.

公开(公告)号：US20230318589A1

公开(公告)日：2023-10-05

申请号：US18127397

申请日：2023-03-28

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Giulio ZOPPI ,  Vincent Pascal ONDE ,  Giuseppe ROMANO

IPC: H03K5/1254 ,  G01D5/347 ,  H03K3/013

CPC classification number: H03K5/1254 ,  G01D5/3473 ,  H03K3/013

Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.