公开(公告)号：US07124502B2

公开(公告)日：2006-10-24

申请号：US10917553

申请日：2004-08-11

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/22

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US07019219B2

公开(公告)日：2006-03-28

申请号：US10899515

申请日：2004-07-26

Applicant: Salvatore Bracaleone

Inventor： Salvatore Bracaleone

IPC: H01B7/08

CPC classification number: H05K1/0245 ,  H01R12/523 ,  H01R13/622 ,  H01R13/746 ,  H01R24/44 ,  H01R24/542 ,  H01R24/56 ,  H01R25/003 ,  H01R2103/00 ,  H01R2107/00 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09636 ,  H05K2201/10356

Abstract: A Quadrax to Twinax conversion apparatus includes stacked trace layers of transmission line with a ground plane between the trace layers. Embodiments include trace layers of stripline or microstrip. Orthogonal plated through holes include a diagonal pair of through holes in electrical contact with traces on one of the trace layers and another diagonal pair of through holes in electrical contact with another trace layer. Contact pins extend through these orthogonal plated through holes with one pair of pins making electrical contact with one trace layer and the other pair of pins making electrical contact with another trace layer. The conversion apparatus electrically connects Twinax cables to respectively different trace layers without crossing over or disturbing the relative positions of the Quadrax diagonal pairs for very efficient high-speed data transfer from four wire Quadrax to two wire Twinax cables.

Abstract translation: Quadrax至Twinax转换装置包括在迹线层之间具有接地平面的传输线的堆叠迹线层。 实施例包括带状线或微带的迹线层。 正交电镀通孔包括与其中一个迹线层上的迹线电接触的对角对对的通孔，以及与另一个迹线层电接触的另一对角线对通孔。 接触销通过这些正交电镀通孔延伸，一对引脚与一个迹线层电接触，另一对引脚与另一个迹线层电接触。 转换装置将Twinax电缆电连接到不同的迹线层，而不会跨越或干扰Quadrax对角线对的相对位置，从而从四线Quadrax到两线双绞线电缆进行非常有效的高速数据传输。

公开(公告)号：US20030121146A1

公开(公告)日：2003-07-03

申请号：US10239731

申请日：2002-11-14

Inventor： Walter Schmidt

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer are and a prefabricated product are placed between a support and a perforation die. The prefabricated product is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die, perforation tips of the perforation die forming microvias for contacting the structures. A surface of the dielectric layer or the prefabricated product is configured or coated to in a manner that the prefabricated product and the dielectric layer stick to each other after the pressure has been applied.

Abstract translation: 根据本发明，将微穿孔（PMP）工艺步骤与层压工艺组合。 为此，介电层和预制产品被放置在支撑件和穿孔模具之间。 预制产品被形成由微孔接触的结构的导电层部分覆盖。 在穿孔模具上施加压力，穿孔模具的穿孔尖端形成用于接触结构的微孔。 在施加压力之后，电介质层或预制产品的表面被构造或涂覆成使得预制产品和电介质层彼此粘合。

公开(公告)号：US4393438A

公开(公告)日：1983-07-12

申请号：US328435

申请日：1981-12-07

Applicant: Robert L. Schelhorn

Inventor： Robert L. Schelhorn

IPC: H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H05K1/18

CPC classification number: H05K3/445 ,  H05K1/053 ,  H05K2201/09636 ,  H05K2201/09881 ,  H05K2201/10416 ,  H05K3/4046

Abstract: In accordance with this invention a porcelain coated metal board is provided which has flat surfaces and further has electrical connections between the face and reverse surfaces of the board. In accordance with a further aspect of this invention the boards of this invention are obtained by a method in which the connecting pins are sealed in a spaced relationship in apertures in the metal core of the board and insulated from the core prior to the application of the porcelain to the surfaces of the core.

Abstract translation: 根据本发明，提供了一种具有平坦表面并且在板的面和反面之间还具有电连接的瓷涂层金属板。 根据本发明的另一方面，本发明的板是通过一种方法获得的，其中连接销在板的金属芯中的孔中以间隔的关系密封，并在施加之前与芯绝缘 瓷器到核心的表面。