中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

153 records (took 0.022 seconds)

    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD
    11.
    发明申请
    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
    超自对准TRENCH-DMOS结构和方法

    公开(公告)号：US20100032751A1

    公开(公告)日：2010-02-11

    申请号：US12189062

    申请日：2008-08-08

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66734 ,  H01L21/2257 ,  H01L29/04 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7813

    Abstract: A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.

    Abstract translation: 半导体器件包括形成在N外延层中的P体层; 形成在P体和N外延层中的沟槽中的栅电极; 由栅极电极旁边的P体层形成的顶部源极区域; 沿着栅电极的侧壁设置在栅电极和源极之间，栅电极和P体之间以及栅电极和N外延层之间的栅极绝缘体; 设置在所述栅电极的顶部的盖绝缘体; 以及沿着源极的侧壁和栅极绝缘体的侧壁设置的N +掺杂的间隔物。 源包括从间隔物扩散的N +掺杂剂。 由N型外延层形成含有P型掺杂剂的体接触区域。 接触区域接触P体层和源的一个或多个P掺杂区域。 还公开了制造这种装置的方法。 本发明的实施例也可以应用于P沟道器件。

    Apparatus and method for high-voltage transient blocking using low voltage elements
    12.
    发明授权
    Apparatus and method for high-voltage transient blocking using low voltage elements 有权
    使用低电压元件的高压瞬态阻塞的装置和方法

    公开(公告)号：US07646576B2

    公开(公告)日：2010-01-12

    申请号：US11271059

    申请日：2005-11-09

    Applicant: Richard A. Harris ,  Francois Hebert

    Inventor： Richard A. Harris ,  Francois Hebert

    IPC: H02H3/20 ,  H02H9/04

    CPC classification number: H02H9/025 ,  H01L27/0266 ,  H01L27/0727 ,  H01L29/808 ,  H02H9/046

    Abstract: An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.

    Abstract translation: 一种用于使用具有与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）的装置和方法，使得瞬态改变偏置电压Vp p沟道器件和n沟道器件的偏置电压Vn一致。 具体地，改变偏置电压，使得p沟道器件和n沟道器件相互切断以阻止瞬变。 耗尽型n沟道器件采用一组级联的低压耗尽型场效应晶体管（FET），例如连接源极到漏极的金属氧化物 - 硅场效应晶体管（MOSFET），以实现所需的高电压工作 的TBU。

    Bottom source LDMOSFET structure and method
    13.
    发明申请
    Bottom source LDMOSFET structure and method 有权
    底源LDMOSFET结构和方法

    公开(公告)号：US20090263947A1

    公开(公告)日：2009-10-22

    申请号：US12456949

    申请日：2009-06-25

    Applicant: Francois Hebert

    Inventor： Francois Hebert

    IPC: H01L21/336

    CPC classification number: H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: This invention discloses a method to form a bottom-source lateral diffusion MOS (BS-LDMOS) device with a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The method includes a step of applying a sinker-channel mask for carrying out a deep sinker multiple energy implant to form a combined sinker-channel region in lower portion of an epitaxial layer to function as a buried source-body contact extending to and contacting a bottom of the substrate functioning as a bottom source electrode.

    Abstract translation: 本发明公开了一种形成底源横向扩散MOS（BS-LDMOS）器件的方法，源极区域设置在半导体衬底的顶表面附近的漏极区域的横向相对的位置，该半导体衬底在源极区域和漏极区域之间支撑栅极 。 该方法包括以下步骤：施加沉降通道掩模，用于进行深沉沉多次能量注入，以在外延层的下部形成组合沉降沟道区，以用作延伸到和接触的外部源体接触 底部的底部用作底部源极。

    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
    14.
    发明申请
    Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
    自对准开槽积分型场效应晶体管（AccuFET）结构及方法

    公开(公告)号：US20090218619A1

    公开(公告)日：2009-09-03

    申请号：US12074280

    申请日：2008-03-02

    Applicant: Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    Inventor： Francois Hebert ,  Madhur Bobde ,  Anup Bhalla

    IPC: H01L29/739 ,  H01L21/3205

    CPC classification number: H01L29/7828 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666

    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

    Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。 半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。 粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。 阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。 这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极 电压Vgs = 0伏。

    Planar split-gate high-performance MOSFET structure and manufacturing method
    15.
    发明申请
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US20090181503A1

    公开(公告)日：2009-07-16

    申请号：US12381813

    申请日：2009-03-16

    Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC: H01L21/337

    CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    Abstract translation: 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

    Planar split-gate high-performance MOSFET structure and manufacturing method
    20.
    发明申请
    Planar split-gate high-performance MOSFET structure and manufacturing method 有权
    平面分闸高性能MOSFET结构及制造方法

    公开(公告)号：US20070278571A1

    公开(公告)日：2007-12-06

    申请号：US11444853

    申请日：2006-05-31

    Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

    IPC: H01L29/94 ,  H01L29/76

    CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.

    Abstract translation: 本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成 分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。 晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻 设备。 晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区 。

Patent Agency Ranking