中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.018 seconds)

    SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION
    11.
    发明申请
    SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION 有权
    选择铜包层沉积

    公开(公告)号：US20110162875A1

    公开(公告)日：2011-07-07

    申请号：US12683857

    申请日：2010-01-07

    Applicant: Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

    Inventor： Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

    IPC: H05K1/09 ,  B05D5/12

    CPC classification number: H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H05K3/282 ,  H05K3/388 ,  H05K3/4682

    Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.

    Abstract translation: 金属互连结构在含铜结构中的铜原子和自对准铜封装层之间提供高粘合强度，其仅选择性地沉积在暴露的铜表面上。 下层金属互连结构包括第一介电材料层和嵌入在下金属衬里中的含铜结构。 在形成含铜结构的平坦化工艺之后，将含铜结构体的露出表面形成Cu-S键的材料施加到含铜结构体的表面。 该材料仅选择性地沉积在暴露的Cu表面上，从而形成自对准的铜封装层，并且对下面的铜表面提供高粘附强度。 随后可以在铜封装层上形成电介质盖层和上层金属互连结构。

    Method and apparatus for controlling local current to achieve uniform plating thickness
    17.
    发明授权
    Method and apparatus for controlling local current to achieve uniform plating thickness 失效
    用于控制局部电流以实现均匀电镀厚度的方法和装置

    公开(公告)号：US06890413B2

    公开(公告)日：2005-05-10

    申请号：US10318607

    申请日：2002-12-11

    Applicant: Tien-Jen Cheng ,  Todd M. Fowler ,  Ajay P. Giri ,  Anton Nenadic ,  Blessen Samuel ,  Keith Kwong Hon Wong

    Inventor： Tien-Jen Cheng ,  Todd M. Fowler ,  Ajay P. Giri ,  Anton Nenadic ,  Blessen Samuel ,  Keith Kwong Hon Wong

    IPC: C25D7/12 ,  C25D5/00 ,  C25D5/02 ,  C25D17/10 ,  C25D17/12 ,  C25D21/12 ,  H01L21/288 ,  H05K3/24

    CPC classification number: H01L21/2885 ,  C25D5/02 ,  C25D17/001 ,  C25D17/007 ,  C25D17/10 ,  C25D17/12 ,  H05K3/241

    Abstract: A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated. The process further includes impressing a current through the electroplating bath between the substrate and the anode, and between the second cathode and the anode, and electroplating the metallic features of different density onto the substrate.

    Abstract translation: 一种用于在基片表面上电镀不同密度的金属特征的方法包括提供具有阳极的电镀浴，将基底浸入与阳极间隔开的电镀浴中，该基底包括阴极。 位于基板和阳极之间并且与基板表面相邻并与基板表面分离的电镀槽中的电镀槽是包括具有与要电镀的金属特征相符的不同尺寸的开口的金属丝网筛分部分的第二阴极。 第二阴极屏蔽部分具有较大尺寸的具有更高密度特征的相邻区域的开口，以进行电镀，并且要电镀较低密度特征的较小尺寸的相邻区域的开口。 该方法进一步包括通过电镀浴在基板和阳极之间以及在第二阴极和阳极之间施加电流，并将不同密度的金属特征电镀到基板上。

    Method for removing copper oxide layer
    18.
    发明授权
    Method for removing copper oxide layer 失效
    去除氧化铜层的方法

    公开(公告)号：US08444868B2

    公开(公告)日：2013-05-21

    申请号：US12695273

    申请日：2010-01-28

    Applicant: Tien-Jen Cheng ,  Stephan Grunow ,  Zhengwen Li ,  Huilong Zhu

    Inventor： Tien-Jen Cheng ,  Stephan Grunow ,  Zhengwen Li ,  Huilong Zhu

    IPC: C23F1/00

    CPC classification number: H01L21/02074 ,  C23G5/00

    Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.

    Abstract translation: 本发明涉及从铜表面去除氧化铜以提供清洁的铜表面的方法，其中所述方法包括将含有氧化铜的铜表面暴露于其中含有羧酸化合物的无水蒸气，其中无水蒸气为 由含有羧酸的无水有机溶液和选自烃和醚溶剂的一种或多种溶剂产生。

    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby
    19.
    发明授权
    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
    形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法

    公开(公告)号：US08373273B2

    公开(公告)日：2013-02-12

    申请号：US13533135

    申请日：2012-06-26

    Applicant: Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    Inventor： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    Abstract translation: 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY
    20.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY 有权
    形成集成电路装置的方法，其具有金属扩散阻挡层和形成的器件的大分子互连

    公开(公告)号：US20120267785A1

    公开(公告)日：2012-10-25

    申请号：US13533135

    申请日：2012-06-26

    Applicant: Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    Inventor： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    Abstract translation: 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

Patent Agency Ranking