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    SEMICONDUCTOR DEVICE WITH INTEGRATED HOT PLATE AND RECESSED SUBSTRATE AND METHOD OF PRODUCTION
    14.
    发明申请
    SEMICONDUCTOR DEVICE WITH INTEGRATED HOT PLATE AND RECESSED SUBSTRATE AND METHOD OF PRODUCTION 有权
    具有一体化热板和基板的半导体器件及其制造方法

    公开(公告)号：US20150303141A1

    公开(公告)日：2015-10-22

    申请号：US14651197

    申请日：2013-12-05

    Applicant: AMS AG

    Inventor： Franz SCHRANK ,  Martin SCHREMS

    IPC: H01L23/528 ,  G01N27/14 ,  G01N33/00 ,  H01L23/522

    CPC classification number: H01L23/528 ,  G01N27/128 ,  G01N27/14 ,  G01N33/0004 ,  G01N33/0016 ,  H01L21/76898 ,  H01L23/345 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/647 ,  H01L27/0629 ,  H01L31/024 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step.

    Abstract translation: 半导体器件包括半导体材料的衬底，衬底上的电介质层，布置在电介质层中的导电接触焊盘，布置在电介质层中的热板，在热板的位置处的衬底的凹部， 以及操作热板的集成电路。 导电层布置在与电介质层相对的衬底的一侧上。 衬底在接触焊盘上方设置有通孔，并且将导电层与接触焊盘连接的导电材料施加在通孔中。 凹槽和通孔在相同的工艺步骤中形成。

    METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE
    15.
    发明申请
    METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE 有权
    生产通过基板的互连的半导体器件的方法

    公开(公告)号：US20140038410A1

    公开(公告)日：2014-02-06

    申请号：US13956274

    申请日：2013-07-31

    Applicant: ams AG

    Inventor： Jochen KRAFT ,  Franz SCHRANK ,  Martin SCHREMS

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.

    Abstract translation: 在具有包括金属平面（5）的金属间电介质（4）和具有绝缘层（2）的相对后表面（15）的主表面（14）上设置半导体基板（1）和导电连接垫 （7）。 在金属间电介质上施加蚀刻停止层（6），以防止在随后的方法步骤期间去除金属平面之上的金属间电介质。 具有侧壁（3）和底部（13）的开口（9）通过连接垫上方的基板从主表面形成。 通过产生并随后部分去除电介质层（11），在侧壁上形成侧壁间隔物（10）。 绝缘层从底部移除以露出连接垫的一个区域。 金属层被施加在开口中并且被提供用于通过基底的互连。

    3D-INTEGRATED OPTICAL SENSOR AND METHOD OF PRODUCING A 3D-INTEGRATED OPTICAL SENSOR
    16.
    发明申请
    3D-INTEGRATED OPTICAL SENSOR AND METHOD OF PRODUCING A 3D-INTEGRATED OPTICAL SENSOR 审中-公开

    公开(公告)号：US20190237500A1

    公开(公告)日：2019-08-01

    申请号：US16312145

    申请日：2017-06-02

    Applicant: ams AG

    Inventor： Hubert Enichlmair ,  Martin SCHREMS ,  Gregor Toschkoff ,  Thomas Bodner ,  Mario Manninger

    IPC: H01L27/146

    CPC classification number: H01L27/14621 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685

    Abstract: A 3D-Integrated optical sensor comprises a semiconductor substrate, an integrated circuit, a wiring, a filter layer, a transparent spacer layer, and an on-chip diffuser. The semiconductor substrate has a main surface. The integrated circuit comprises at least one light sensitive area and is arranged in the substrate at or near the main surface. The wiring provides an electrical connection to the integrated circuit and is connected to the integrated circuit. The wiring is arranged on or in the semiconductor substrate. The filter layer has a direction dependent transmission characteristic and is arranged on the integrated circuit. In fact, the filter layer at least covers the light sensitive area. The transparent spacer layer is arranged on the main surface and, at least partly, encloses the filter layer. A spacer thickness is arranged to limit a spectral shift of the filter layer. The on-chip diffuser is arranged on the transparent spacer layer.

    METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER
    19.
    发明申请
    METHOD OF APPLICATION OF A CARRIER TO A DEVICE WAFER 审中-公开
    将载体应用于器件滤波器的方法

    公开(公告)号：US20150340264A1

    公开(公告)日：2015-11-26

    申请号：US14759400

    申请日：2014-01-08

    Applicant: AMS AG

    Inventor： Joerg SIEGERT ,  Martin SCHREMS ,  Jochen KRAFT ,  Franz SCHRANK

    IPC: H01L21/683 ,  H01L21/768

    CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10

    Abstract: A device wafer having a main surface including an edge region and a carrier having a further main surface including an annular surface region corresponding to the edge region of the device wafer are provided. An adhesive is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer.

    Abstract translation: 提供了具有包括边缘区域的主表面和具有包括对应于器件晶片的边缘区域的环形表面区域的另外的主表面的载体的器件晶片。 粘合剂施加在边缘区域和/或环形表面区域中，但不施加在主表面的剩余区域上。 器件晶片通过粘合剂固定到载体上。 当装置晶片被固定到载体上时，主表面和另外的主表面彼此接触，而主表面和另外的主表面仅在边缘区域彼此紧固。 在进一步的工艺步骤之后，器件晶片从载体上移除，其可以包括在器件晶片中形成贯通晶片通孔。

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