公开(公告)号：US20150194307A1

公开(公告)日：2015-07-09

申请号：US14147666

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Churamani GAIRE ,  Bharat KRISHNAN ,  Jin Ping LIU

IPC: H01L21/02 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both.

Abstract translation: 提供了制造应变翅片结构的方法，其包括：在衬底结构上提供虚拟衬底材料，虚拟衬底材料具有虚拟衬底晶格常数和虚拟衬底晶格结构; 在所述虚拟衬底材料的区域上提供第一材料，所述第一材料部分地通过符合所述虚拟衬底晶格结构获得应变的第一材料晶格结构; 并将第一鳍图案蚀刻到第一材料中。 该方法可以包括在虚拟衬底材料的第二区域上提供第二材料，第二材料部分地通过符合虚拟衬底晶格结构并且将鳍状图案蚀刻到第二材料中来获得应变晶格结构。 所得到的装置可以具有拉伸应变翅片结构或压缩应变翅片结构，或两者。

公开(公告)号：US20150035018A1

公开(公告)日：2015-02-05

申请号：US13955861

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L21/306

CPC classification number: H01L27/0924 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一个中间半导体器件包括例如：具有至少一个具有至少一个通道的鳍片的衬底; 通道上至少有一个门; 在门上至少有一个硬掩模; 以及设置在栅极和硬掩模上的至少一个间隔物。 一种方法包括，例如：获得中间半导体器件; 将至少一个凹部形成到所述基底中，所述凹部包括底部和暴露所述至少一个翅片的一部分的至少一个侧壁; 将介电层沉积到所述至少一个凹部中; 去除所述电介质层的至少一部分以形成阻挡介电层; 以及在所述阻挡介电层上的所述至少一个凹槽中进行选择性外延生长。

公开(公告)号：US20150017774A1

公开(公告)日：2015-01-15

申请号：US13938786

申请日：2013-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Hong YU ,  Jin Ping LIU ,  Hyucksoo YANG ,  Lun ZHAO ,  Chandra REDDY

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/823431 ,  H01L29/7854

Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.

Abstract translation: 提供了在制造半导体器件期间使用的热氧化处理方法和工艺。 一种方法包括例如：获得具有蚀刻到该装置中的至少一个腔的装置; 对所述至少一个腔进行热氧化处理; 以及清洁所述至少一个腔。 一个过程包括例如：提供具有衬底的半导体器件，衬底上的至少一个层和至少一个鳍; 在翅片上形成至少一个闸门; 掺杂鳍片以下的至少一个区域; 在该装置上施加间隔层; 蚀刻间隔层以露出栅极材料的至少一部分; 将空腔蚀刻到所述至少一个翅片中; 将成形的开口蚀刻到空腔中; 在所述至少一个腔体上进行热氧化处理; 以及在腔的内表面上生长至少一个外延层。

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US20160284540A1

公开(公告)日：2016-09-29

申请号：US14666787

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir RAY ,  Yiqun LIU ,  Jin Ping LIU ,  Fabio D'ADDAMIO ,  Sandeep GAAN

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/12

CPC classification number: H01L21/02181 ,  C23C16/308 ,  G11C11/22 ,  H01L21/02189 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Abstract translation: 提供了一种半导体器件，其包括半导体衬底和包含二氧化铪（HfO 2）和二氧化锆（ZrO 2）中的一种或两者的10至40厚的高k电介质层。 高k电介质层设置在半导体衬底上，并且其包含至少一些四方相HfO 2和/或四方相ZrO 2。 还提供了制造半导体器件的方法以及采用该半导体器件的电子器件。

公开(公告)号：US20160190324A1

公开(公告)日：2016-06-30

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US20160111320A1

公开(公告)日：2016-04-21

申请号：US14515628

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang SHEN ,  Zhenyu HU ,  Jin Ping LIU

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract translation: 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US20160099344A1

公开(公告)日：2016-04-07

申请号：US14928057

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Jing WAN ,  Andy WEI

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

公开(公告)号：US20150364336A1

公开(公告)日：2015-12-17

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Haigou HUANG ,  Jin Ping LIU ,  Huang LIU

IPC: H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。

公开(公告)号：US20150333067A1

公开(公告)日：2015-11-19

申请号：US14812500

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.