公开(公告)号：US09831174B1

公开(公告)日：2017-11-28

申请号：US15168899

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/02244 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76864 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53252 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US09824921B1

公开(公告)日：2017-11-21

申请号：US15202817

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US09666791B2

公开(公告)日：2017-05-30

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/08 ,  H01L21/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

公开(公告)号：US09613906B2

公开(公告)日：2017-04-04

申请号：US14311457

申请日：2014-06-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76853 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76868 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.

公开(公告)号：US09391140B2

公开(公告)日：2016-07-12

申请号：US14309956

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xunyuan Zhang ,  Catherine B. Labelle

IPC: H01L21/8242 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract translation: 提供一种制造凸起翅片结构的方法，所述制造方法包括：在衬底上提供衬底和至少一个电介质层; 在所述至少一个电介质层中形成沟槽，所述沟槽具有下部，侧部和上部，所述上部至少部分地从所述下部向外偏移并且通过所述侧部与所述下部 一部分; 并且在沟槽中生长材料以形成凸起的翅片结构，其中形成沟槽以确保沟槽的下部中的任何生长缺陷终止于沟槽的下部或横向部分，并且不延伸 进入沟槽的上部。

公开(公告)号：US20160133572A1

公开(公告)日：2016-05-12

申请号：US14536083

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xunyuan Zhang ,  Wei Lin

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/02244 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process through an overall masking layer to define an opening in a layer of insulating material, wherein the overall masking layer is comprised of a patterned metal-silicate masking layer that is positioned on and in contact with the layer of insulating material and a patterned masking layer positioned on and in contact with the patterned metal-silicate masking layer, over-filling the opening with a conductive material and performing at least one planarization process so as to remove excess materials positioned outside of the opening above the patterned metal-silicate masking layer and thereby define a conductive structure that is positioned in the opening.

Abstract translation: 本文中公开的一种说明性方法包括通过整体掩模层进行至少一个蚀刻工艺以限定绝缘材料层中的开口，其中整个掩模层由图案化的金属硅酸盐掩蔽层 定位在绝缘材料层上并与绝缘材料层接触并且与图案化的金属硅酸盐掩蔽层定位并与其接触的图案化掩模层，用导电材料过度填充该开口并执行至少一个平坦化处理以便去除 多余材料位于图案化的金属硅酸盐掩蔽层上方的开口的外侧，从而限定位于开口中的导电结构。

公开(公告)号：US09263327B2

公开(公告)日：2016-02-16

申请号：US14310314

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Sean X. Lin

IPC: H01L21/768 ,  H01L21/288

CPC classification number: H01L21/288 ,  C23C18/1834 ,  C23C18/40 ,  C23C18/405 ,  H01L21/76874 ,  H01L21/76877

Abstract: Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.

Abstract translation: 提供了电路结构制造方法，其包括：图案化设置在衬底结构上的电介质层内的至少一个开口; 在介电层的至少一个开口内提供衬垫材料; 在衬垫材料的至少一部分上设置表面活性剂; 以及使用无电镀方法在所述衬里材料上沉积导电材料以形成导电结构，并且所述设置的表面活性剂抑制在所述导电结构内形成空隙。

公开(公告)号：US09236299B2

公开(公告)日：2016-01-12

申请号：US14201255

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

公开(公告)号：US20150171086A1

公开(公告)日：2015-06-18

申请号：US14630504

申请日：2015-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。