公开(公告)号：US20160254641A1

公开(公告)日：2016-09-01

申请号：US15056794

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: H01S5/022 ,  H01S5/183

CPC classification number: H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

Abstract translation: 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。

公开(公告)号：US09242854B2

公开(公告)日：2016-01-26

申请号：US14137538

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sarah K. Haney ,  Weng Hong Teh ,  Feras Eid ,  Sasha N. Oster

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0041 ,  B81B7/0032 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00293 ,  B81C1/00539 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/0136 ,  B81C2203/0792

Abstract: Embodiments of the invention describe hermetic encapsulation for MEMS devices, and processes to create the hermetic encapsulation structure. Embodiments comprise a MEMS substrate stack that further includes a magnet, a first laminate organic dielectric film, a first hermetic coating disposed over the magnet, a second laminate organic dielectric film disposed on the hermetic coating, a MEMS device layer disposed over the magnet, and a plurality of metal interconnects surrounding the MEMS device layer. A hermetic plate is subsequently bonded to the MEMS substrate stack and disposed over the formed MEMS device layer to at least partially form a hermetically encapsulated cavity surrounding the MEMS device layer. In various embodiments, the hermetically encapsulated cavity is further formed from the first hermetic coating, and at least one of the set of metal interconnects, or a second hermetic coating deposited onto the set of metal interconnects.

Abstract translation: 本发明的实施例描述了用于MEMS器件的气密封装和用于创建气密封装结构的工艺。 实施例包括进一步包括磁体的MEMS基板堆叠，第一层压有机介电膜，设置在磁体上的第一密封涂层，设置在密封涂层上的第二层压有机绝缘膜，设置在磁体上的MEMS器件层，以及 围绕MEMS器件层的多个金属互连。 密封板随后结合到MEMS衬底叠层并且设置在所形成的MEMS器件层上，以至少部分地形成围绕MEMS器件层的气密封装的腔体。 在各种实施例中，气密封装的空腔进一步由第一密封涂层形成，并且该组金属互连中的至少一个或沉积在该组金属互连件上的第二密封涂层。

公开(公告)号：US20190393180A1

公开(公告)日：2019-12-26

申请号：US16561965

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/50 ,  H01L25/16 ,  H01L23/538

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US10083936B2

公开(公告)日：2018-09-25

申请号：US15289058

申请日：2016-10-07

Applicant: INTEL CORPORATION

Inventor： Weng Hong Teh ,  John S. Guzek ,  Shan Zhong

IPC: H01L25/065 ,  H01L23/12 ,  H01L23/498 ,  H01L23/13 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

公开(公告)号：US20170053887A1

公开(公告)日：2017-02-23

申请号：US15255351

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract translation: 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US20170025392A1

公开(公告)日：2017-01-26

申请号：US15289058

申请日：2016-10-07

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  John S. GUZEK ,  Shan ZHONG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Abstract translation: 描述了封装组件和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建立结构，使得能够例如三维（3D）封装（或封装（SiP）或多芯片模块系统）），片上3D封装和混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器和逻辑到逻辑接口堆叠组件。

公开(公告)号：US09520376B2

公开(公告)日：2016-12-13

申请号：US14875247

申请日：2015-10-05

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/538 ,  H01L23/36 ,  H01L21/56 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

公开(公告)号：US20150189797A1

公开(公告)日：2015-07-02

申请号：US14126271

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Sarah Haney ,  Weng Hong Teh ,  Feras Eid

IPC: H05K9/00 ,  B81B7/02 ,  B32B38/10 ,  H05K1/11 ,  B32B37/24 ,  B81B7/00 ,  G06F1/18

CPC classification number: H05K9/0052 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/243 ,  B32B2457/00 ,  B81B7/0029 ,  B81B7/0032 ,  B81B7/02 ,  B81C1/0023 ,  G06F1/182 ,  H01L21/568 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H05K1/115 ,  Y10T156/10 ,  H01L2924/00

Abstract: Magnetic field shielding material with high relative permeability incorporated into a build-up package, for example to restrict a field of a magnet integrated with the build-up to a target device configured to operate in the field. In embodiments, a first device is physically coupled to the build-up. In embodiments, a magnetic field shielding material is disposed in contact with the build-up and in proximity to the first device to restrict a magnetic field either to a region occupied by the first device or to a region exclusive of the first device. A field shielding material may be disposed within build-up near a permanent magnet also within the build-up to reduce exposure of another device, such as an IC, to the magnetic field without reducing MEMS device exposure.

Abstract translation: 具有高的相对磁导率的磁场屏蔽材料被并入到积聚封装中，例如将与积聚物集成的磁体的场限制到被配置为在现场操作的目标装置。 在实施例中，第一设备物理地耦合到建立。 在实施例中，磁场屏蔽材料设置成与积层接触并且靠近第一装置，以将磁场限制到由第一装置占据的区域或不包括第一装置的区域。 场屏蔽材料也可以在堆积物内的永磁体附近的堆积内设置，以减少诸如IC之类的其它器件（例如IC）的暴露，而不会降低MEMS器件的暴露。

公开(公告)号：US20150104907A1

公开(公告)日：2015-04-16

申请号：US14570785

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/00 ,  H01L23/34 ,  H01L21/56

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US08866287B2

公开(公告)日：2014-10-21

申请号：US13631990

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Vinodhkumar Raghunathan

IPC: H01L23/12

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract translation: 描述了包括基板及其制造的电子组件。 一个组件包括嵌入在多层基板中的电介质层中的管芯，以及嵌入多层基板中的介电层中的电介质区域。 多层基板包括裸片侧和接地侧，第一介电区和电介质层延伸到管芯侧。 多个通孔位于第一电介质区域内，通孔延伸到管芯侧的焊盘。 描述和要求保护其他实施例。