公开(公告)号：US20140264612A1

公开(公告)日：2014-09-18

申请号：US13834514

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  THOMAS N. ADAM

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/088 ,  H01L21/02104 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls. To further increase the thickness of the epitaxial semiconductor region, the method may cycle between depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls; and removing the amorphous portions on the sidewalls until the combined thickness of all the crystalline portions reaches a desired thickness.

Abstract translation: 实施例包括具有弯曲顶面的外延源/漏区及其形成方法。 根据示例性实施例，具有弯曲顶表面的外延半导体区域可以通过提供具有由半导体材料制成的基本平坦的底部的区域和基本上垂直于平面底部的非半导体材料制成的侧壁形成，沉积半导体层 通过使用氮载气的低压化学气相沉积工艺，在平坦的底部上具有结晶部分和侧壁上的非晶部分，以及从侧壁去除非晶部分。 为了进一步增加外延半导体区域的厚度，该方法可以在沉积在平坦底部上具有结晶部分的半导体层和侧壁上的非晶部分之间循环; 并除去侧壁上的非晶部分，直到所有结晶部分的组合厚度达到期望的厚度。

公开(公告)号：US20230189656A1

公开(公告)日：2023-06-15

申请号：US17643594

申请日：2021-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SABA ZARE ,  MICHAEL RIZZOLO ,  THEODORUS E. STANDAERT ,  ALEXANDER REZNICEK

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L25/065

CPC classification number: H01L43/08 ,  H01L27/226 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L25/0657

Abstract: A semiconductor device is provided. The semiconductor device includes a first electrode; an MRAM stack formed on the first electrode; a hardmask structure formed on the MRAM stack; a conductive etch stop layer formed around the hardmask structure; and a second electrode formed on the hardmask structure.

公开(公告)号：US20170170277A1

公开(公告)日：2017-06-15

申请号：US15175609

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： KARTHIK BALAKRISHNAN ,  KANGGUO CHENG ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/1037 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprising a substrate, an base layer disposed on the substrate having a thickness C in first area and a thickness B in a second area and a hole extending to the substrate filled with semiconductor, a first semiconductor fin disposed on the first area and having a height A, and a second semiconductor fin disposed on the second area and having a height D, wherein (A+C)=(B+D).

公开(公告)号：US20170081781A1

公开(公告)日：2017-03-23

申请号：US15371366

申请日：2016-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOAR-TABARI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: C30B25/04 ,  C30B25/14 ,  H01L21/3065 ,  C30B33/12 ,  H01L21/02 ,  C30B25/18 ,  C30B29/06

CPC classification number: C30B25/04 ,  C30B25/105 ,  C30B25/14 ,  C30B25/183 ,  C30B25/186 ,  C30B29/06 ,  C30B33/12 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065

Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

公开(公告)号：US20160172498A1

公开(公告)日：2016-06-16

申请号：US15049796

申请日：2016-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  RAMACHANDRA DIVAKARUNI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  SOON-CHEON SEO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

公开(公告)号：US20150041853A1

公开(公告)日：2015-02-12

申请号：US13965178

申请日：2013-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  POUYA HASHEMI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/22 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/02565 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/22 ,  H01L29/267

Abstract: A structure including a compound semiconductor layer epitaxially grown on an epitaxial oxide layer is provided wherein the lattice constant of the epitaxial oxide layer may be different from the semiconductor substrate on which it is grown. Fabrication of one structure includes growing a graded semiconductor layer stack to engineer a desired lattice parameter on a semiconductor substrate or layer. The desired compound semiconductor layer is formed on the graded layer. The epitaxial oxide layer is grown on and lattice matched to the desired layer. Fabrication of an alternative structure includes growing a layer of desired compound semiconductor material directly on a germanium substrate or a germanium layer formed on a silicon substrate and growing an epitaxial oxide layer on the layer of the desired material. Following implantation of a cleavage layer and wafer bonding to a handle wafer, the layer of desired compound semiconductor material is fractured along the cleavage layer and the residual portion thereof removed. A layer of the desired compound semiconductor material is then regrown on the epitaxial oxide layer.

Abstract translation: 提供包括在外延氧化物层上外延生长的化合物半导体层的结构，其中外延氧化物层的晶格常数可以不同于其生长的半导体衬底。 一种结构的制造包括生长渐变半导体层堆叠以在半导体衬底或层上工程化所需的晶格参数。 所需的化合物半导体层形成在渐变层上。 外延氧化物层生长并与所需层晶格匹配。 替代结构的制造包括直接在锗衬底或形成在硅衬底上的锗层上生长所需化合物半导体材料层，并在所需材料层上生长外延氧化物层。 在将切割层和晶片结合植入到处理晶片之后，期望的化合物半导体材料层沿着切割层断裂，并且其残留部分被去除。 然后将所需化合物半导体材料的层再生长在外延氧化物层上。

公开(公告)号：US20150028454A1

公开(公告)日：2015-01-29

申请号：US13950173

申请日：2013-07-24

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  GHAVAM G. SHAHIDI

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract translation: 在半导体晶片或其它基板上形成硅和硅锗翅片，以便于产生紧密间隔的nFET和pFET器件。 在形成填充凹部的硅锗层的外延生长之前，使用图案化心轴层在晶片中形成一个或多个凹槽。 间隔件形成在图案化心轴层的侧壁上，随后移除心轴层。 蚀刻在间隔物之间​​的晶片和硅锗层的暴露区域以形成可用于来自晶片的nFET器件的鳍片和可用于来自硅锗层的pFET器件的鳍片。

公开(公告)号：US20230086681A1

公开(公告)日：2023-03-23

申请号：US17482426

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUILONG XIE ,  CHRISTOPHER J WASKIEWICZ ,  ALEXANDER REZNICEK ,  SU CHEN FAN ,  HENG WU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-κ metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.

公开(公告)号：US20180258549A1

公开(公告)日：2018-09-13

申请号：US15976224

申请日：2018-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOAR-TABARI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: C30B25/04 ,  H01L21/02 ,  H01L21/3065 ,  C30B25/18 ,  C30B29/06 ,  C30B25/14 ,  C30B25/10 ,  C30B33/12

CPC classification number: C30B25/04 ,  C30B25/105 ,  C30B25/14 ,  C30B25/183 ,  C30B25/186 ,  C30B29/06 ,  C30B33/12 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065

Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

公开(公告)号：US20180047828A1

公开(公告)日：2018-02-15

申请号：US15235829

申请日：2016-08-12

Applicant: International Business Machines Corporation

Inventor： OLEG GLUSCHENKOV ,  SANJAY C. MEHTA ,  SHOGO MOCHIZUKI ,  ALEXANDER REZNICEK

IPC: H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66666 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.