公开(公告)号：US10241912B2

公开(公告)日：2019-03-26

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/0811 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00 ,  G06F12/0895

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20190042122A1

公开(公告)日：2019-02-07

申请号：US15856173

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F3/06

CPC classification number: H04L9/0819 ,  G06F3/0604 ,  G06F3/0605 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/0632 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0683 ,  G06F3/0685 ,  G06F9/28 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/445 ,  G06F9/4494 ,  G06F9/5044 ,  G06F9/5088 ,  G06F12/023 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/14 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F15/161 ,  G06F15/17331 ,  G06F16/119 ,  G06F16/221 ,  G06F16/2237 ,  G06F16/2255 ,  G06F16/2282 ,  G06F16/2365 ,  G06F16/2453 ,  G06F16/2455 ,  G06F16/24553 ,  G06F16/248 ,  G06F16/25 ,  G06F16/9014 ,  G06F2201/85 ,  G06F2209/509 ,  G06F2212/1044 ,  G06F2212/1052 ,  G06F2212/601 ,  G06F2213/0064 ,  G11C8/12 ,  G11C29/028 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  H04L9/0894 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L41/0893 ,  H04L41/0896 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/30 ,  H04L49/351 ,  H04L49/9005 ,  H04L69/12 ,  H04L69/22 ,  H04L69/32 ,  H04L69/321

Abstract: Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to provision memory to a compute sled. Further, the memory pool controller maps, in response to the request, each of the memory devices of the memory pool to the compute sled. The memory pool controller additionally assigns access rights to the compute sled as a function of one or more memory characteristics of the compute sled. The memory characteristics are indicative of an amount of memory in the memory pool to be used by the compute sled and the access rights are indicative of access permissions to one or more memory address ranges associated with the one or more memory devices.

公开(公告)号：US20190035483A1

公开(公告)日：2019-01-31

申请号：US15859367

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G11C29/38 ,  G11C29/36 ,  G11C29/44 ,  G06F3/06

Abstract: Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty.

公开(公告)号：US20170186661A1

公开(公告)日：2017-06-29

申请号：US14998123

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Russell S. Aoki ,  Jonathan W. Thibado ,  Jeffory L. Smalley ,  David J. Llapitan ,  Thomas A. Boyd ,  Harvey R. Kofstad ,  Dimitrios Ziakas ,  Hongfei Yan

IPC: H01L23/34 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L23/4006 ,  H01L23/49816 ,  H01L23/49822 ,  H05K1/0212 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2203/176

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

公开(公告)号：US09015388B2

公开(公告)日：2015-04-21

申请号：US13930643

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Murugasamy Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

IPC: G06F3/06 ,  G06F12/14 ,  G06F21/57 ,  G06F13/38

CPC classification number: G06F12/1408 ,  G06F21/575 ,  G06F21/78

Abstract: In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.

Abstract translation: 在一个实施例中，计算设备可以包括控制单元。 控制单元可以从包含在计算设备中的中央处理单元（CPU）获取可能正在执行与计算设备相关联的基本输入/输出系统（BIOS）的请求。 请求可以包括对可能表示包含在计算设备中的存储的最大授权存储大小的值的请求。 控制单元可以生成值并将值发送到CPU。 CPU可以基于该值生成系统地址映射。 CPU可以将系统地址映射发送到控制单元，控制单元可以基于所获取的系统地址映射来获取系统地址映射并且配置包含在计算设备中的地址解码器。

公开(公告)号：US12282366B2

公开(公告)日：2025-04-22

申请号：US17443374

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Dimitrios Ziakas ,  Rita D. Gupta

IPC: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  H04L12/10

Abstract: In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.

公开(公告)号：US10469252B2

公开(公告)日：2019-11-05

申请号：US15856173

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: H04L9/08 ,  G06F3/06 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/24 ,  H04L29/06 ,  H04L29/08 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F9/50 ,  G06F17/50 ,  G06F16/25 ,  G06F16/2453 ,  G06F16/11 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for efficiently managing the allocation of memory in a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to provision memory to a compute sled. Further, the memory pool controller maps, in response to the request, each of the memory devices of the memory pool to the compute sled. The memory pool controller additionally assigns access rights to the compute sled as a function of one or more memory characteristics of the compute sled. The memory characteristics are indicative of an amount of memory in the memory pool to be used by the compute sled and the access rights are indicative of access permissions to one or more memory address ranges associated with the one or more memory devices.

公开(公告)号：US10331614B2

公开(公告)日：2019-06-25

申请号：US15025988

申请日：2013-11-27

Applicant: INTEL CORPORATION ,  Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

Inventor： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC: G06F11/00 ,  G06F15/78 ,  G06F11/10 ,  G06F11/34 ,  G06F11/16

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

公开(公告)号：US20190065231A1

公开(公告)日：2019-02-28

申请号：US15859388

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski ,  Dimitrios Ziakas

IPC: G06F9/455 ,  G06F9/48

Abstract: Technologies for migrating virtual machines (VMs) includes a plurality of compute sleds and a memory sled each communicatively coupled to a resource manager server. The resource manager server is configured to identify a compute sled of a for a virtual machine instance, allocate a first set of resources of the identified compute sled for the VM instance, associate a region of memory in a memory pool of a memory sled with the compute sled, and create the VM instance on the compute sled. The resource manager server is further configured to migrate the VM instance to another compute sled, associate the region of memory in the memory pool with the other compute sled, and start-up the VM instance on the other compute sled. Other embodiments are described herein.

公开(公告)号：US20160239460A1

公开(公告)日：2016-08-18

申请号：US15025988

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC: G06F15/78 ,  G06F11/16

CPC classification number: G06F15/7803 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F11/1662 ,  G06F11/3485 ,  G06F2201/805

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract translation: 实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。 这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。 相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。 该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入端可通信地耦合到布置在前端或后端装载机架中的至少一些NVM /存储模块 /输出（I / O）通道。 通过采用可以在计算机系统的前端或后端加载接收的NVM /存储模块，系统和方法提供了存储器组件在实现常规服务器架构的计算机系统中无法实现的可维护性。