公开(公告)号：US20130049195A1

公开(公告)日：2013-02-28

申请号：US13215959

申请日：2011-08-23

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/488 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

Abstract translation: 一种方法包括执行激光切槽以去除晶片中的电介质材料以形成沟槽，其中沟槽从晶片的顶表面延伸以在晶片的顶表面和底表面之间的中间水平处停止。 沟槽在晶片中的两个相邻芯片之间的划线中。 将聚合物填充到沟槽中，然后固化。 在固化聚合物的步骤之后，执行模锯以分离两个相邻的芯片，其中模具的切口线切割填充在沟槽中的聚合物的一部分。

公开(公告)号：US09620430B2

公开(公告)日：2017-04-11

申请号：US13356173

申请日：2012-01-23

Applicant: Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

Inventor： Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US08871568B2

公开(公告)日：2014-10-28

申请号：US13345485

申请日：2012-01-06

Applicant: Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/58 ,  H01L23/485 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/83

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract translation: 一种方法包括在衬底上形成电介质层，在电介质层上形成互连结构，以及将管芯结合到互连结构。 然后去除衬底，并对电介质层进行图案化。 连接器形成在电介质层的表面，其中连接器电耦合到管芯。

公开(公告)号：US08828848B2

公开(公告)日：2014-09-09

申请号：US13328746

申请日：2011-12-16

Applicant: Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.

Abstract translation: 提供具有沿侧壁的凸缘的模具和形成模具的方法。 还提供了一种包装模具的方法。 通过形成具有第一宽度的第一凹口，然后在第一凹口内形成第二凹槽，使得第二凹槽具有小于第一宽度的第二宽度，来切割诸如经处理晶片的基底。 第二凹口延伸穿过衬底，从而切割衬底。 第一宽度和第二宽度之间的宽度差导致沿着骰子的侧壁的凸缘。 骰子可以放置在基底上，例如插入物，以及放置在骰子和基底之间的底部填充物。 凸缘防止或减少底部填充物在相邻骰子之间的距离。 可以在基材上形成模塑料。

公开(公告)号：US20130187258A1

公开(公告)日：2013-07-25

申请号：US13356173

申请日：2012-01-23

Applicant: Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

Inventor： Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L27/06 ,  H01L21/78

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract translation: 一种方法包括将第一和第二包装部件接合在第三包装部件的顶表面上，并分配聚合物。 聚合物包括在第一和第三包装部件之间的空间中的第一部分，在第二和第三包装部件之间的空间中的第二部分和第一和第二包装部件之间的间隙中的第三部分。 然后在聚合物上进行固化步骤。 在固化步骤之后，将聚合物的第三部分锯切以在第一和第二包装部件之间形成沟槽。

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US09406500B2

公开(公告)日：2016-08-02

申请号：US13369138

申请日：2012-02-08

Applicant: I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： I-Ting Chen ,  Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/02041 ,  H01L21/4864 ,  H01L21/67028 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Abstract translation: 助焊剂残渣清洁系统包括第一和第二浸没室，第一和第二喷雾室以及干燥室。 当晶片浸入第一化学品中时，第一浸入室软化在介于晶片和管芯之间的微胶片周围形成的焊剂残余物的外部区域。 当晶片通过第一化学喷雾撞击以暴露焊剂残留物的内部区域时，第一喷雾室除去焊剂残余物的外部区域。 当晶片浸入第二种化学品中时，第二浸入室软化助焊剂残余物的内部区域。 当晶片被第二化学喷雾冲击时，第二喷雾室去除焊剂残余物的内部区域，以便将晶​​片清洁至预定的标准。 干燥室干燥晶片。

公开(公告)号：US09245773B2

公开(公告)日：2016-01-26

申请号：US13369126

申请日：2012-02-08

Applicant: Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

Inventor： Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Abstract translation: 公开了半导体器件封装方法及其结构。 在一个实施例中，封装半导体器件的方法包括将多个第二管芯耦合到第一管芯的顶表面，以及确定多个第二管芯和第一管芯之间的距离。 该方法还包括基于确定的距离来确定在第一模具和第一模具中的每一个之间配置的底部填充材料的量，以及将确定量的底部填充材料设置在多个第二模具的每一个下。

公开(公告)号：US09064879B2

公开(公告)日：2015-06-23

申请号：US13228244

申请日：2011-09-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

Abstract translation: 公开了利用新颖的芯片附着膜的半导体器件的封装方法和结构。 在一个实施例中，封装半导体器件的方法包括提供载体晶片并且在载体晶片上形成包括聚合物的管芯附着膜（DAF）。 多个模具附接到DAF，并且多个管芯被封装。 至少载体晶片从封装的管芯移除，并且封装的管芯被切割。

公开(公告)号：US09024438B2

公开(公告)日：2015-05-05

申请号：US13192756

申请日：2011-07-28

Applicant: Cheng-Lin Huang ,  I-Ting Chen ,  Ying Ching Shih ,  Po-Hao Tsai ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Cheng-Lin Huang ,  I-Ting Chen ,  Ying Ching Shih ,  Po-Hao Tsai ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13011 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01053 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A conductive bump structure of a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprises a regular body, and each of a second subset of the conductive bumps comprises a ring-shaped body.

Abstract translation: 半导体器件的导电凸块结构包括包括主表面的衬底和分布在衬底的主表面上的导电凸块。 导电凸块的第一子集中的每一个包括规则体，并且导电凸块的第二子集中的每一个包括环形体。