公开(公告)号：US09601435B2

公开(公告)日：2017-03-21

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  David Fraser Rae ,  Rajneesh Kumar ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/16 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

公开(公告)号：US12293980B2

公开(公告)日：2025-05-06

申请号：US16870642

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun Yeon ,  Suhyung Hwang ,  Chin-Kwan Kim ,  Rajneesh Kumar ,  Darryl Sheldon Jessie

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q5/307 ,  H01Q9/16 ,  H01Q21/06

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

公开(公告)号：US20240107665A1

公开(公告)日：2024-03-28

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/4644 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10015 ,  H05K2201/10734

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

公开(公告)号：US20210366838A1

公开(公告)日：2021-11-25

申请号：US16879517

申请日：2020-05-20

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Rajneesh Kumar ,  Jeongil Jay Kim ,  Chin-Kwan Kim

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01Q1/22 ,  H01Q1/52

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

公开(公告)号：US10403707B2

公开(公告)日：2019-09-03

申请号：US15476823

申请日：2017-03-31

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Joonsuk Park

IPC: H01F17/00 ,  H01L49/02 ,  H01F17/04 ,  H01F27/29

Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.

公开(公告)号：US20170098634A1

公开(公告)日：2017-04-06

申请号：US15097719

申请日：2016-04-13

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L25/10 ,  H04W4/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H04W4/00 ,  H04W4/80 ,  H01L2924/00012

Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer. The package on package (PoP) device includes a gap controller located between the first package and the second package.

公开(公告)号：US09370097B2

公开(公告)日：2016-06-14

申请号：US13783168

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Kuiwon Kang ,  Omar James Bchir

IPC: H05K7/10 ,  H05K1/11 ,  G01R31/28 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，多个迹线具有100微米（μm）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。

公开(公告)号：US09159670B2

公开(公告)日：2015-10-13

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L21/4763 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US20140356635A1

公开(公告)日：2014-12-04

申请号：US13967186

申请日：2013-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim

IPC: H05K1/02 ,  H05K3/44

CPC classification number: H05K1/0271 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3511 ,  H05K1/0306 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/31678 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.

Abstract translation: 一些新颖特征涉及一种衬底，其包括第一芯层，横向位于衬底中的第一芯层的第二芯层，侧向位于第一芯层之间的第一无机芯层（例如，玻璃，硅，陶瓷） 和第二芯层，被配置为与被配置为耦合到基板的管芯垂直对准的第一无机芯层，以及覆盖第一芯层，第二芯层和第一无机芯层的电介质层。 在一些实施方案中，第一无机核心层具有第一热膨胀系数（CTE），所述管芯具有第二热膨胀系数，并且所述第一核心层具有第三热膨胀系数（CTE）。 第一无机芯层的第一CTE与模具的第二CTE紧密匹配，以减少翘曲的可能性。

公开(公告)号：US20140322868A1

公开(公告)日：2014-10-30

申请号：US14328618

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Milind Pravin Shah ,  Houssam Wafic Jomaa ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L23/00 ,  H05K1/09

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83192 ,  H05K1/092 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括管芯，耦合到管芯的凹凸金属化（UBM）结构和阻挡层。 UBM结构具有第一氧化物性质。 阻挡层具有比UBM结构的第一氧化物性质更能抵抗从焊剂材料中去除氧化物的第二氧化物性质。 阻挡层包括顶部，底部和侧部。 顶部连接到UBM结构，并且侧部被基本氧化。