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    Self-aligned top contact for MRAM fabrication
    11.
    发明授权
    Self-aligned top contact for MRAM fabrication 有权
    用于MRAM制造的自对准顶部接触

    公开(公告)号：US09318696B2

    公开(公告)日：2016-04-19

    申请号：US14195566

    申请日：2014-03-03

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang ,  Shiqun Gu

    IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

    CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

    Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

    Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。

    Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)
    14.
    发明授权
    Small form factor magnetic shield for magnetorestrictive random access memory (MRAM) 有权
    用于磁致伸缩随机存取存储器（MRAM）的小尺寸磁屏蔽

    公开(公告)号：US08952504B2

    公开(公告)日：2015-02-10

    申请号：US13777475

    申请日：2013-02-26

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

    IPC: H01L23/552 ,  H01L43/02

    CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

    Abstract translation: 一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。 芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。 通孔包括铁磁材料。 在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。 在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。 在一些实施方案中，通孔通过衬底通孔。 在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。

    LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER
    15.
    发明申请
    LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER 审中-公开
    包含氧化层的低成本间隙器

    公开(公告)号：US20140306349A1

    公开(公告)日：2014-10-16

    申请号：US13861086

    申请日：2013-04-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Shiqun Gu ,  Urmi Ray ,  Roawen Chen ,  Brian Matthew Henderson ,  Ratibor Radojcic ,  Matthew Nowak ,  Nicholas Yu

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.

    Abstract translation: 一些实施方案提供了一种插入器，其包括衬底，衬底中的通孔和氧化层。 通孔包括金属材料。 氧化层位于通孔和衬底之间。 在一些实施方式中，衬底是硅衬底。 在一些实施方案中，氧化层是通过将基底暴露于热而形成的热氧化物。 在一些实施方案中，氧化层被配置为在通孔和基底之间提供电绝缘。 在一些实施方案中，插入件还包括绝缘层。 在一些实施方案中，绝缘层是聚合物层。 在一些实现中，插入器还包括在插入器的表面上的至少一个互连。 所述至少一个互连件位于所述插入件的表面上，使得所述氧化层位于所述互连件和所述基板之间。

    DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE
    16.
    发明申请
    DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE 有权
    用于测试半导体连续性的DAISY链接连接

    公开(公告)号：US20140264331A1

    公开(公告)日：2014-09-18

    申请号：US13800976

    申请日：2013-03-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M. Nowak ,  Glen T. Kim ,  Mark C. Chan ,  Shiqun Gu

    IPC: H01L21/66

    CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

    Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。

    Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection
    17.
    发明授权
    Voltage switchable dielectric for die-level electrostatic discharge (ESD) protection 有权
    用于芯片级静电放电（ESD）保护的电压可切换电介质

    公开(公告)号：US08691707B2

    公开(公告)日：2014-04-08

    申请号：US13956703

    申请日：2013-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

    IPC: H01L21/31

    CPC classification number: H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

    Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

    Abstract translation: 可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。 电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。 当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。 因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。 电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。 一种方法包括在第一端子和第二端子之间的第一管芯上沉积可电压切换介电层。

    High density fan out package structure
    20.
    发明授权
    High density fan out package structure 有权

    公开(公告)号：US10157823B2

    公开(公告)日：2018-12-18

    申请号：US14693820

    申请日：2015-04-22

    Applicant: QUALCOMM Incorporated

    Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

    IPC: H01L23/48 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

    Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

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