公开(公告)号：US09847422B2

公开(公告)日：2017-12-19

申请号：US15290269

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US09595446B2

公开(公告)日：2017-03-14

申请号：US14150906

申请日：2014-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chungsun Lee ,  Jung-Hwan Kim ,  Kwang-chul Choi ,  Un-Byoung Kang ,  Jeon Il Lee

IPC: H01L21/46 ,  H01L21/302 ,  H01L21/683 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/302 ,  H01L21/02057 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68368 ,  H01L21/78 ,  H01L2224/81

Abstract: Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.

Abstract translation: 提供了处理衬底的方法。 该方法可以包括在衬底和载体之间提供结合层，以将衬底粘合到载体上，在衬底被载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 接合层可以包括热固性胶层和设置在热固性胶层的相对侧上的热固性剥离层。

公开(公告)号：US08969939B2

公开(公告)日：2015-03-03

申请号：US13960434

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/792 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US11711920B2

公开(公告)日：2023-07-25

申请号：US17076306

申请日：2020-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/27 ,  H01L21/02

CPC classification number: H10B43/27 ,  H10B41/27 ,  H01L21/02233

Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

公开(公告)号：US10943918B2

公开(公告)日：2021-03-09

申请号：US16516756

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US09793291B2

公开(公告)日：2017-10-17

申请号：US15142365

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jin Shin ,  Hong-Suk Kim ,  Jung-Hwan Kim ,  Sang-Hoon Lee ,  Hun-Hyeong Lim ,  Yong-Seok Cho ,  Young-Dae Kim ,  Han-Vit Yang

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11568 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

公开(公告)号：US09589947B2

公开(公告)日：2017-03-07

申请号：US14566685

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihwan Hwang ,  Young Kun Jee ,  Jung-Hwan Kim ,  Tae Hong Min ,  Kwang-chul Choi

IPC: H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract translation: 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。

公开(公告)号：US20160381729A1

公开(公告)日：2016-12-29

申请号：US15193894

申请日：2016-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Phil LEE ,  Jung-Hwan Kim ,  Kang-Je Noh ,  Jong-Jin Bae ,  Yong-Gil Han

IPC: H04W76/02 ,  H04L29/12 ,  H04L29/06

CPC classification number: H04W76/18

Abstract: Disclosed is a communication method that prevents excess message transmission and improves the efficiency of a communication system. The method includes transmitting a first connection request message for a service connection to a network by an electronic device, receiving a first connection reject message for the first connection request from the network, abstaining from retransmission of the connection request to the network based on the first connection reject message, determining whether an operation configured in the electronic device belongs to a condition set by the electronic device based on at least a portion of the abstinence operation, and when determining that the operation belongs to the condition, transmitting a second connection request message to the network.

Abstract translation: 公开了防止多余的消息传输并提高通信系统的效率的通信方法。 该方法包括：通过电子设备向网络发送用于服务连接的第一连接请求消息，从网络接收第一连接请求的第一连接拒绝消息，基于第一连接请求拒绝连接请求重新发送到网络 连接拒绝消息，基于所述禁欲操作的至少一部分，确定所述电子设备中配置的操作是否属于由所述电子设备设置的条件，并且当确定所述操作属于所述条件时，发送第二连接请求消息 到网络。

公开(公告)号：US09023716B2

公开(公告)日：2015-05-05

申请号：US14147718

申请日：2014-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chungsun Lee ,  Jung-Seok Ahn ,  Kwang-chul Choi ,  Un-Byoung Kang ,  Jung-Hwan Kim ,  Joonsik Sohn ,  Jeon Il Lee

IPC: H01L21/58 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L21/6835 ,  B32B37/1284 ,  B32B37/18 ,  B32B37/24 ,  B32B37/26 ,  B32B38/04 ,  B32B38/10 ,  B32B38/162 ,  B32B2037/268 ,  B32B2315/08 ,  B32B2457/14 ,  H01L21/02057 ,  H01L21/02126 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13023 ,  H01L2924/12042 ,  H01L2924/181 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract translation: 一种处理衬底的方法包括：在衬底和载体之间提供接合层，以将衬底粘合到载体上，在衬底由载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 粘合层可以包括热固性剥离层和热固性胶层，其中至少一个热固性胶层设置在热固性剥离层的每一侧上。

公开(公告)号：US20130267057A1

公开(公告)日：2013-10-10

申请号：US13909160

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC: H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘合图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。