公开(公告)号：US20130187263A1

公开(公告)日：2013-07-25

申请号：US13738082

申请日：2013-01-10

Applicant: Xintec Inc.

Inventor： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

IPC: H01L21/78 ,  H01L23/12

CPC classification number: H01L21/78 ,  B81C1/00888 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.

Abstract translation: 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。

公开(公告)号：US09437478B2

公开(公告)日：2016-09-06

申请号：US14339360

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Ho-Yin Yiu

IPC: H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00 ,  H01L23/00 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract translation: 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09355975B2

公开(公告)日：2016-05-31

申请号：US14339355

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Chi-Chang Liao

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L29/06 ,  H01L23/525 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3701 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的芯片的芯片封装。 芯片包括与上表面相邻的信号焊盘区域。 第一凹部沿着侧壁从上表面向下表面延伸。 至少一个第二凹部从第一凹部的第一底部向下表面延伸。 第一和第二凹部沿着上表面的侧面进一步横向延伸，并且沿着侧面延伸的第一凹部的长度大于沿着侧面延伸的第二凹部的长度。 再分配层电连接到信号焊盘区域并延伸到第二凹槽中。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09355970B2

公开(公告)日：2016-05-31

申请号：US14958155

申请日：2015-12-03

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L29/00 ,  H01L23/58 ,  H01L21/48 ,  H01L21/78 ,  H01L21/283

CPC classification number: H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。

公开(公告)号：US09349710B2

公开(公告)日：2016-05-24

申请号：US14504319

申请日：2014-10-01

Applicant: XINTEC INC.

Inventor： Chien-Hui Chen ,  Tsang-Yu Liu ,  Chun-Wei Chang ,  Chia-Ming Cheng

IPC: H01L21/50 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

Abstract translation: 提供一种形成芯片封装的方法。 提供第一基板。 第二衬底附接在第一衬底上，其中第二衬底具有由划线区域分隔的多个矩形芯片区域。 去除对应于划线区域的第二衬底的一部分，以在第一衬底上形成多个芯片，其中在相邻芯片之间形成至少一个桥接部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US09318461B2

公开(公告)日：2016-04-19

申请号：US14255872

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chun-Wei Chang ,  Kuei-Wei Chen ,  Chia-Ming Cheng ,  Chia-Sheng Lin ,  Chien-Hui Chen ,  Tsang-Yu Liu

IPC: H01L21/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/784 ,  H01L21/683

CPC classification number: H01L24/26 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract translation: 提供晶片级的芯片阵列。 晶片级的芯片阵列包括半导体晶片和至少一个延伸线保护。 半导体晶片具有彼此相邻布置的至少两个芯片和载体层。 每个芯片具有上表面和下表面，并且包括至少一个装置。 该装置设置在上表面上，被载体层覆盖。 延伸线保护设置在载体层之下和两个芯片之间。 延长线保护的厚度小于芯片的厚度。 其中延伸线保护件中至少有一条延伸线。 此外，还提供了由晶片级阵列芯片制造的芯片封装及其方法。

公开(公告)号：US09165890B2

公开(公告)日：2015-10-20

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shih-Chin Chen ,  Yi-Ming Chang ,  Chien-Hui Chen ,  Chia-Ming Cheng ,  Wei-Luen Suen ,  Chen-Han Chiang

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。