公开(公告)号：US20170053848A1

公开(公告)日：2017-02-23

申请号：US15237287

申请日：2016-08-15

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Po-Chang HUANG ,  Tsang-Yu LIU ,  Yu-Lung HUANG ,  Chi-Chang LIAO

IPC: H01L23/31 ,  H01L23/08 ,  G06K9/00 ,  H01L21/56

CPC classification number: H01L23/3121 ,  G06K9/00013 ,  G06K9/0002 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/11

Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.

Abstract translation: 提供感测模块。 感测模块​​包括感测装置。 感测装置包括具有第一表面和与其相对的第二表面的第一基底。 感测装置还包括与第一表面相邻的感测区域和第一表面上的导电垫片。 感测装置还包括在第二表面上的再分配层，并且电连接到导电垫。 感测模块​​还包括结合到感测装置的第二基板和盖板，使得感测装置在第二基板和盖板之间。 导电焊盘通过再分布层与第二基板电连接。 感测模块​​还包括填充在第二基板和盖板之间以封装感测装置的封装层。

公开(公告)号：US20160379040A1

公开(公告)日：2016-12-29

申请号：US15177143

申请日：2016-06-08

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: G06K9/00 ,  G06F3/041

CPC classification number: G06K9/00013 ,  G06F3/041 ,  G06F2203/04103

Abstract: This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.

Abstract translation: 本发明提供了一种触摸面板感测芯片封装模块复合体，包括：具有第一顶表面和彼此相对的第一底表面的触摸面板，其中所述第一底表面具有第一腔体，所述第一腔体具有被侧壁包围的底壁 ; 形成在所述底壁和与所述空腔相邻的所述第一底面的着色层; 以及通过形成在腔的底壁上的着色层与腔体结合的芯片尺度感测芯片封装模块。

公开(公告)号：US20140332983A1

公开(公告)日：2014-11-13

申请号：US14339341

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US20140332908A1

公开(公告)日：2014-11-13

申请号：US14339360

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN ,  Ho-Yin YIU

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract translation: 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20140073089A1

公开(公告)日：2014-03-13

申请号：US14077877

申请日：2013-11-12

Applicant: XINTEC INC.

Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG

IPC: H01L25/00

CPC classification number: H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US20130126086A1

公开(公告)日：2013-05-23

申请号：US13741318

申请日：2013-01-14

Applicant: XINTEC INC.

Inventor： Wen-Cheng CHIEN ,  Ching-Yu NI ,  Shu-Ming CHANG

IPC: B05D1/36

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

公开(公告)号：US20130045571A1

公开(公告)日：2013-02-21

申请号：US13673656

申请日：2012-11-09

Applicant: XINTEC INC.

Inventor： Wei-Ming CHEN ,  Shu-Ming CHANG

IPC: H01L21/60

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US20230049126A1

公开(公告)日：2023-02-16

申请号：US17980507

申请日：2022-11-03

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US20220285423A1

公开(公告)日：2022-09-08

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Chaung-Lin LAI

IPC: H01L27/146 ,  H01L23/544

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US20210210445A1

公开(公告)日：2021-07-08

申请号：US17140952

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.